Senior Physical Design Architect – FPGA Backend

Altera; San Jose (CA); On-site; USD 149,100 - 215,000; Full time

Job summary

Altera, a leading FPGA solutions provider, seeks a Senior Physical Design Engineer to drive backend implementation from RTL to GDSII for FPGA/SoC devices. You will work with architecture, CAD/EDA, and manufacturing teams to meet performance, power, and area goals while advancing PD flows and automation.

Ideal candidates have 10+ years in digital PD, strong scripting (Tcl, Python), and expertise with Synopsys and Cadence toolchains.

Qualifications

• 10+ years of hands-on experience in digital ASIC and/or SoC physical design including synthesis, floorplanning, place-and-route, CTS, routing, ECOs, and signoff
• 8+ years using industry-standard EDA tools (IC Compiler II, Fusion Compiler, Innovus, PrimeTime, StarRC, Calibre)
• 5+ years scripting/automation using Tcl for PD flow
• 2+ years Python/Perl/Shell for PD productivity
• 5+ years in floorplanning, power planning, placement, CTS, routing, timing closure, ECOs, signoff
• 5+ years in low-power PD methodologies (clock gating, multi-power domain, UPF/CPF)
• 5+ years in TI/IR drop, EM, SI, and PD verification (DRC/LVS/ERC)
• 5+ years in PD signoff with RTL/Architecture/CAD/Manufacturing teams
• 3+ years in chip integration: block integration, pin assignment, timing/constraint push-down
• 2+ years in bump/RDL routing, MiM caps, ESD signoff
• 2+ years in IO budgeting across chip/partition/block levels

Responsibilities

• Lead physical design tasks from netlist to GDSII for FPGA/SoC devices
• Apply PPA optimization across blocks or full-chip hierarchies
• Collaborate with FE design, architecture, CAD/EDA, and manufacturing teams to meet constraints
• Develop and improve PD flows, scripts, and automation frameworks (TCL, Python, Perl)
• Participate in timing, power, EM/IR, SI, DRC/LVS/ERC verification and sign-off readiness
• Integrate FPGA-specific PD aspects: CLB placement, fabric routing, IO ring optimization, power domains
• Work with manufacturing/packaging to ensure manufacturability and yield targets
• Mentor junior engineers and contribute to flows, reviews, and process improvements

Skills

Scripting & automation

Python

Tcl

Programming concepts

Education

Bachelor's degree in Electrical or Computer Engineering

Master's degree (preferred)

Tools

Synopsys IC Compiler II

Synopsys Fusion Compiler

Cadence Innovus

Cadence Encounter

Synopsys PrimeTime

Synopsys StarRC

Mentor Calibre

Job description

Altera, a leading FPGA solutions provider, seeks a Senior Physical Design Engineer to drive backend implementation from RTL to GDSII for FPGA/SoC devices. You will work with architecture, CAD/EDA, and manufacturing teams to meet performance, power, and area goals while advancing PD flows and automation.

Ideal candidates have 10+ years in digital PD, strong scripting (Tcl, Python), and expertise with Synopsys and Cadence toolchains.