Senior PCB & Silicon Packaging Architect

Arm Limited; Chandler (AZ); Hybrid; USD 250,000 - 338,000; Full time

Job summary

Arm is seeking an Electronics Engineer specializing in PCB and silicon packaging co-design to join the Packaging, Boards and Multiphysics team. You will collaborate with SoC teams, architects and platform leads to define requirements and features for embedded compute platforms around Arm's latest IP.

The role focuses on PCB development alongside the chip packaging team, evaluating routing strategies, design rules and layer trade-offs to deliver reliable, cost-effective solutions; strong SI/PI

Qualifications

• Deep technical background in SoC architectures and embedded compute.
• Experience with high-speed IO standards and peripherals.
• PCB layout and packaging integration experience.
• Familiarity with PCB fabrication, stackup and substrates.
• Ability to influence pin-outs for cost optimization.
• Experience collaborating with packaging teams.
• Strong communication across geographies.

Responsibilities

• Collaborate with engineering groups to specify, evaluate and develop solutions for PCB and silicon package integration.
• Drive PCB development alongside the chip packaging team, including routing strategies and layer optimization.
• Translate technology requirements into platform architectures and communicate concepts across audiences.
• Provide timescale estimates and justifications into the program team.

Skills

SoC architectures

High-speed IO

PCB design

Signal integrity

Power integrity

Packaging collaboration

EDA tools

Tools

Cadence OrCAD

Allegro

Job description

Arm is seeking an Electronics Engineer specializing in PCB and silicon packaging co-design to join the Packaging, Boards and Multiphysics team. You will collaborate with SoC teams, architects and platform leads to define requirements and features for embedded compute platforms around Arm's latest IP.

The role focuses on PCB development alongside the chip packaging team, evaluating routing strategies, design rules and layer trade-offs to deliver reliable, cost-effective solutions; strong SI/PI