Senior Package Thermal-Mechanical Engineer

ChipAdd Corp.; City of Binghamton (NY); On-site; USD 120,000 - 155,000; Full time

Benefits offered by this job

Equity

Medical, dental and vision coverage

Paid time off

Competitive base salary

Job summary

CHIPADD is based in Binghamton, NY, near the birthplace of IBM, with leadership in Silicon Valley. Our culture runs on curiosity, execution and a deep commitment to the mission.

Senior Package Thermal-Mechanical Engineer role shapes designs and materials choices, runs FEA models for chip/package/board assemblies, and leads qualification to JEDEC and IPC standards while translating customer reliability needs into test plans.

Qualifications

• MS or PhD in Mechanical Engineering, Materials Science or a related field.
• 5-7 years of experience in thermomechanical modeling and design of semiconductor packages or device-level electronics.
• Experience with nonlinear material models and solder fatigue modeling.

Responsibilities

• Build and run finite element models of chip, package and board assemblies for thermal and thermomechanical behavior.
• Model solder joint fatigue under thermal cycling and mechanical loading, predicting lifetime.
• Guide cooling design and characterize material properties for models.

Skills

Thermal-Mechanical modeling

FEA expertise

Problem solving

Cross-functional collaboration

Technical presentation

Education

MS or PhD in Mechanical Engineering or Materials Science

Tools

Ansys Mechanical

Abaqus

CSAM

X-ray

CT

SEM/EDS

Dye-and-pry

Job description

Senior Package Thermal-Mechanical Engineer

• Employment type: Full-time
• Salary range: $120,000 - 155,000 per year + equity

When copper meets silicon, physics gets opinionated. You'll be the one who predicts exactly what happens next, and proves it.

About CHIPADD

CHIPADD is based in Binghamton, NY, close to the original birthplace of IBM, and we have leadership based in Silicon Valley as well. Our culture runs on curiosity, execution and a deep commitment to the mission.

The Role

Your work will shape our designs, our materials choices and the reliability data our customers need before they put our technology on their most valuable chips.

What You'll Do

• Build and run finite element analysis (FEA) models of chip, package and board assemblies, covering thermal, thermomechanical stress, warpage and coupled thermal-structural behavior
• Model chip-level and board-level solder joint fatigue under thermal cycling, power cycling and mechanical loading, and predict lifetime using established fatigue and creep models
• Guide the design of CHIPADD's cooling designs
• Characterize and select materials, and build the material property data our models depend on, including CTE, modulus, creep, fatigue and temperature-dependent behavior of copper, silicon, solders, underfills and polymers
• Apply deep knowledge of electronics assembly (flip chip, BGA, lidding, underfill, reflow and SMT) to keep designs manufacturable and reliable
• Define and run qualification plans to industry standards, including JEDEC (such as JESD22 temperature cycling, HAST, HTS and moisture sensitivity) and IPC, and translate customer reliability requirements into test plans
• Lead forensic failure analysis, including cross-sectioning, SEM/EDS, dye-and-pry and fractography, to find the true root cause and feed it back into design
• Use nondestructive testing methods such as scanning acoustic microscopy (CSAM), X-ray and CT, shadow moiré and digital image correlation to detect defects and validate models
• Correlate simulations with test data so our models become a trusted design tool, and present results to customers and partners

What You Bring

• MS or PhD in Mechanical Engineering, Materials Science or a related field
• 5-7 years of experience in thermomechanical modeling and design of semiconductor packages or device-level electronics
• Expert-level FEA skills with tools such as Ansys Mechanical or Abaqus, including nonlinear material models, viscoplastic solder behavior and submodeling
• Proven experience modeling chip-level and board-level solder fatigue and correlating predictions with test results
• Strong knowledge of material properties and behavior for semiconductor packaging materials
• Hands-on knowledge of electronics assembly processes and their impact on reliability
• Experience planning and running JEDEC and IPC qualification of electronics technologies
• Track record of forensic failure analysis and root-cause investigations
• Experience with nondestructive testing methods such as CSAM, X-ray/CT and warpage measurement

Bonus Points

• Experience with liquid cooling, cold plates, lids or thermal interface materials for CPUs, GPUs or AI accelerators
• Experience with advanced packaging such as 2.5D/3D, chiplets, large-die flip chip or wafer-level packaging
• Experience with additively manufactured or porous metal structures
• Scripting for simulation automation and data analysis (Python, APDL or similar)
• Publications or patents in electronic packaging reliability

Who Thrives Here

Hungry. You want the hard problem, and you'd rather ship a working prototype on Friday than a perfect slide deck next month.

Humble. You let the data win the argument, especially when it disagrees with you.

Smart. You learn fast, think from first principles and know when to go deep versus when to move.

Hands-on. You have a track record of building real things that work, and you have the scars (and the spreadsheets) to prove it.

Data-driven. You design experiments, instrument everything and make decisions from the numbers.

What We Offer

• Competitive base salary plus meaningful early-stage equity
• Medical, dental and vision coverage and paid time off
• A seat at the table on a technology that could become the industry standard
• Southern Tier New York living: short commutes, four real seasons, Finger Lakes weekends and an affordable cost of living

Equal opportunity employer