Senior IC Packaging & Layout Architect

Amazon; Tempe (AZ); On-site; USD 159,000 - 215,000; Full time

Job summary

Annapurna Labs is seeking a Sr. Package Layout Engineer to lead end-to-end physical design of advanced IC packages for next‑generation ML and data center ASICs.

You will own the package layout from floor planning through tape-out, collaborating with silicon, SI/PI, thermal, and manufacturing teams to deliver production-ready designs. You will mentor junior layout engineers, ensure DFM compliance, and partner with OSATs and foundries to achieve impedance control and high-yield packaging solutions

Qualifications

• Bachelor's degree in Electrical Engineering or a related field.
• 10+ years of IC package layout and physical design experience.
• Proven track record delivering package designs from concept to tape-out.
• Hands-on with package layout tools such as Cadence APD/SiP, Synopsys IC Packaging, Mentor Xpedition, or equivalent.
• Deep knowledge of advanced packaging: 2.5D/3D-IC, RDL, TSV, and interconnects.
• Experience with OSAT partners and foundries for NPI and yield improvements.

Responsibilities

• Lead the full package layout cycle from die floor planning to tape out release.
• Drive physical design of advanced packaging architectures including 2.5D/3D-IC and fan‑out WLP.
• Define and optimize package floorplans with die placement, power/ground distribution, and high-speed routing.
• Perform detailed RDL and substrate routing for high-density interconnects.
• Collaborate with ASIC physical design teams to co-optimize die-package interfaces for power and signal integrity.
• Drive cross‑level layout co‑optimization across die RDL, interposer/substrate, and PCB levels.

Skills

IC package layout

Physical design

Bump map definition

Escape routing

Power/ground plane design

Impedance control

DFM compliance

Education

Bachelor's degree in Electrical Engineering

Master's degree or equivalent

Tools

Cadence APD/SiP

Synopsys IC Packaging

Mentor Xpedition

Job description

Annapurna Labs is seeking a Sr. Package Layout Engineer to lead end-to-end physical design of advanced IC packages for next‑generation ML and data center ASICs.

You will own the package layout from floor planning through tape-out, collaborating with silicon, SI/PI, thermal, and manufacturing teams to deliver production-ready designs. You will mentor junior layout engineers, ensure DFM compliance, and partner with OSATs and foundries to achieve impedance control and high-yield packaging solutions