Principal ASIC Design Verification Engineer - Terawave

Blue Origin; San Diego (CA); On-site; USD 170,000 - 250,000; Full time

Job summary

Blue Origin in San Diego, CA is seeking a Principal Modem PHY IP Design Verification Engineer to lead verification of advanced modem PHY IP for the Terawave program. You will develop verification strategies, build scalable environments, and collaborate with PHY architects, RTL designers, firmware, FPGA, and validation teams across simulation, emulation, prototyping, and silicon bring-up phases.

The ideal candidate combines strong digital design verification skills with a solid understanding of

Qualifications

• The ideal candidate combines strong digital design verification skills with a solid understanding of modem PHY and DSP systems.

Responsibilities

• Develop and execute verification strategy and plans for modem PHY IP and subsystem-level integration.
• Build and maintain block-level and subsystem-level verification environments for PHY IP using industry-standard methodologies.

Job description

Application close date: Applications will be accepted on an ongoing basis until the requisition is closed.

At Blue Origin, we envision millions of people living and working in space for the benefit of Earth. We’re working to develop reusable, safe, and low-cost space vehicles and systems within a culture of safety, collaboration, and inclusion. Join our team of problem solvers as we add new chapters to the history of spaceflight!

Blue Origin is pioneering the future of space-based communications with TeraWave, a revolutionary satellite communications network designed to deliver symmetrical data speeds of up to 6 Tbps anywhere on Earth. This multi-orbit constellation will consist of optically interconnected satellites in low Earth orbit (LEO) and medium Earth orbit (MEO), providing enterprise-grade connectivity for critical operations worldwide.

We are seeking a Principal Modem PHY IP Design Verification Engineer to lead and execute verification of advanced modem PHY IP for the Terawave program. This role is responsible for developing robust verification strategies, building scalable verification environments, and ensuring high-quality modem PHY IP delivery for next-generation wireless ASIC platforms.

The ideal candidate combines strong digital design verification skills with a solid understanding of modem PHY and DSP systems. This engineer will work closely with PHY architects, RTL designers, systems engineers, firmware, FPGA, and validation teams to verify functionality, performance, and integration of modem PHY IP across simulation, emulation, prototyping, and silicon bring-up phases.

Responsibilities

· Develop and execute verification strategy and plans for modem PHY IP and subsystem-level integration.

· Build and maintain block-level and subsystem-level verification environments for PHY IP using industry-standard methodologies.