Senior Modem ATE Test Engineer Lead High-Volume SoC Tests

Amazon Inc.; San Diego (CA); On-site; USD 185,000 - 250,000; Full time

Job summary

Amazon Leo is seeking a Senior Modem ATE Test Engineer to own end-to-end digital ATE test development for complex SoCs and modem devices. You will lead pattern development, characterization, and production release on Advantest 93K and Teradyne UltraFLEX platforms, working with internal teams and suppliers to optimize test methodology.

You will drive testability and manufacturability in AI/SoC designs, mentor junior engineers, and contribute to reducing test time and cost across digital and DC

Qualifications

• Bachelor's degree in electrical or computer engineering.
• 7+ years in digital ATE test development for high-volume manufacturing.
• Experience with complex SoCs and modem/wireless devices in advanced nodes (7nm+).
• Experience with Advantest 93K and Teradyne UltraFLEX platforms.

Responsibilities

• Develop, debug, and release digital test programs for ASIC/SoC and modem devices on Advantest 93K and Teradyne UltraFLEX.
• Build and debug scan/ATPG test content for complex devices.
• Implement MBIST and memory repair flows.
• Characterize silicon performance and process variation with ring oscillator tests.
• Test and debug high-speed SERDES/HSIO, including eye/jitter tests.
• Convert test patterns to tester formats and validate on hardware.
• Lead device correlation between wafer sort and final test to resolve issues.

Skills

Digital ATE test development

JTAG/boundary-scan

DFT/DFM

Advantest 93K

Teradyne UltraFLEX

SerDes test 100G+

Python scripting

Wafer sort testing

Education

Bachelor's degree in Electrical/Computer Engineering

Tools

Advantest 93K

Teradyne UltraFLEX

Job description

Amazon Leo is seeking a Senior Modem ATE Test Engineer to own end-to-end digital ATE test development for complex SoCs and modem devices. You will lead pattern development, characterization, and production release on Advantest 93K and Teradyne UltraFLEX platforms, working with internal teams and suppliers to optimize test methodology.

You will drive testability and manufacturability in AI/SoC designs, mentor junior engineers, and contribute to reducing test time and cost across digital and DC