Senior AMS Verification Engineer

Platform Recruitment; Austin (TX); On-site; USD 150,000 - 190,000; Full time

Job summary

Platform Recruitment's client is seeking a Senior Mixed-Signal Verification Engineer to own verification of analog/mixed-signal subsystems at the heart of high-speed IO. You will shape sign-off decisions that determine what ships to tape-out, with a small elite team and meaningful equity.

Expect hands-on AMS modeling (Verilog-AMS, real-number modeling), SystemVerilog assertions, and self-checking testbenches.

Qualifications

• BS/MS in Electrical Engineering or related field.
• 5+ years of analog/mixed-signal verification on complex SoCs or mixed-signal IP.
• Hands-on expertise with AMS modeling and verification: Verilog-AMS, real-number modeling, and analog-digital co-simulation flows.
• Proficiency in SystemVerilog with assertion-based verification and self-checking testbench architecture.
• Demonstrated ability to model analog blocks and validate against transistor-level references.

Responsibilities

• Own verification strategy and test plans for mixed-signal subsystems, block level through top-level integration.
• Define modeling approach and fidelity tiers (real-number model vs. Verilog-AMS vs. transistor-level co-sim) and the associated accuracy/runtime trade-offs.
• Build self-checking testbenches for analog/digital interactions — loop convergence, mode transitions, clock-domain crossings.
• Drive AMS co-simulation flows and define functional coverage targeting analog corner behavior.
• Debug and root-cause failures across the analog/digital boundary through to closure.
• Own block- and subsystem-level sign-off for tape-out, including coverage closure.

Skills

AMS modeling

Verilog-AMS

SystemVerilog

Assertion-based verification

Self-checking testbench

Debug skills

Education

BS/MS in Electrical Engineering

Tools

Verilog-AMS tooling

Python scripting

Job description

We're working with a very well-funded, deeply technical semiconductor company building next-generation silicon for high-performance AI compute - a new architecture rather than an iteration on existing designs. Backed by top-tier investors and moving fast toward first customer silicon, this is ground-floor work on hardware that doesn't exist anywhere else yet.

They're looking for a Senior Mixed-Signal Verification Engineer to own verification of the analog and mixed-signal subsystems at the heart of their high-speed IO - the boundary where analog behavior meets digital control. This is one of the hardest and highest-leverage problems in the design flow.

The Role

You'll own verification of high-speed IO RX/TX chains — CDRs, phase interpolators and clock generation, equalization, samplers and slicers, deserializers — and the digital control loops wrapped around them. The goal: find bugs in silicon-accurate simulation, not in the lab.

What Sets This Role Apart

• Ground-floor impact on a genuinely new chip architecture, not legacy silicon
• Real ownership - your sign-off decisions determine what ships to tape-out
• High technical bar, small elite team, very well capitalized with a clear path to first customer silicon

Responsibilities

• Own verification strategy and test plans for mixed-signal subsystems, block level through top-level integration
• Define modeling approach and fidelity tiers (real-number model vs. Verilog-AMS vs. transistor-level co-sim) and the associated accuracy/runtime trade-offs
• Build self-checking testbenches for analog/digital interactions — loop convergence, mode transitions, clock-domain crossings
• Drive AMS co-simulation flows and define functional coverage targeting analog corner behavior
• Debug and root-cause failures across the analog/digital boundary through to closure
• Own block- and subsystem-level sign-off for tape-out, including coverage closure

Requirements

• BS/MS in Electrical Engineering or related field, with 5+ years of analog/mixed-signal verification on complex SoCs or mixed-signal IP
• Hands-on expertise with AMS modeling and verification: Verilog-AMS, real-number modeling, and analog-digital co-simulation flows
• Proficiency in SystemVerilog with assertion-based verification and self-checking testbench architecture
• Demonstrated ability to model analog blocks and validate against transistor-level references
• Strong debug skills across the analog/digital boundary

Nice to have

• Strong working knowledge of high-speed SerDes/wireline architectures
• UVM or other constrained-random, metric-driven verification experience
• Scripting for regression and flow automation (Python, TCL, Make)
• Track record of mixed-signal IP sign-off through tape-out, plus silicon bring-up

Package & Process

Compensation is highly competitive with meaningful equity — genuine ownership in the outcome, not just a salary. Additional benefits include a location-based proximity bonus and employer-contributed retirement plans.

The interview process is rigorous and technical, consistent with the caliber of engineering team you'd be joining.