Senior Mixed-Signal IC Layout Designer

Cirrus Logic; Phoenix (AZ); On-site; USD 120,000 - 180,000; Full time

Job summary

Cirrus Logic in Phoenix, AZ, seeks an experienced IC layout engineer to join our high-performance mixed-signal team. You will collaborate with design engineers to complete layout verification for CMOS ICs using Cadence Virtuoso XL and Mentor Calibre, producing topological layouts for optimal circuit performance.

The ideal candidate has 10+ years in IC layout, an Associates degree in Electronics/IC CAD, and familiarity with common centroid, matching, ESD, latch-up, and IR drop.

Qualifications

• Associates Degree in IC layout CAD; 10+ years of layout experience.
• Ability to layout analog circuitry in a size/time constrained environment.
• Understand layout techniques such as common centroid, matching, isolation, shielding, and dummy devices.
• Strong knowledge of ESD, latch-up, STI, WPE, electromigration, IR drop, cross-coupling.
• Proficiency in floor planning activities with block assembly, and block-level routing.
• LVS trouble shooting and debug skills.
• Proven track record of working in a fast-paced team-oriented environment.
• Great teammate and works well with others

Responsibilities

• Solve layout design issues and proactively intervene.
• Collaborate with design engineers to achieve efficient circuit performance.
• Design analog & mixed-signal layouts.
• Understand device matching techniques.
• Understand signal conditioning/protection techniques.
• Strong collaboration skills, including written and verbal communication.
• Outstanding layout planning and integration skills.
• Experience in routing at the block level and chip top-level using assisted/automated tools

Skills

IC layout

Analog/mixed-signal layout

Floor planning

Block-level routing

Communication

Team collaboration

Problem solving

Education

Associates Degree in Electronic/IC layout CAD specialization

BS Degree in Electronics Engineering

Tools

Cadence Virtuoso XL

Mentor Calibre

Layout CAD tools

Foundry PDKs

Job description

Cirrus Logic in Phoenix, AZ, seeks an experienced IC layout engineer to join our high-performance mixed-signal team. You will collaborate with design engineers to complete layout verification for CMOS ICs using Cadence Virtuoso XL and Mentor Calibre, producing topological layouts for optimal circuit performance.

The ideal candidate has 10+ years in IC layout, an Associates degree in Electronics/IC CAD, and familiarity with common centroid, matching, ESD, latch-up, and IR drop.