Senior Memory Validation Engineer — HBM/GDDR Lead

NVIDIA Corporation; United States; On-site; USD 168,000 - 259,000; Full time

Job summary

NVIDIA is seeking a senior hardware engineer to lead memory subsystem enablement from first silicon to production. You will work with HBM/GDDR, drive test plans, and collaborate across ASIC, board, and software teams.

The role requires 10+ years in high-speed DRAM design and test, plus hands-on hardware and software skills. Equity and comprehensive benefits are offered. Applications close 2026-11-03.

Qualifications

• Masters or higher in Electrical engineering (or equivalent).
• 10+ years of hands-on experience in high-speed DRAM design and test.
• Broad comprehension of ASIC design, mixed signal design, and power/signal integrity concepts.
• Strong fundamentals in science, engineering, and data analysis.
• Very comfortable being hands-on with hardware and software.
• Working knowledge of Linux, scripting, programming, computer systems, and data analysis methods.

Responsibilities

• Lead HBM/GDDR enablement, validation, and failure analysis for NVIDIA's datacenter and graphics products.
• Drive review of memory partner's design limits and test methodology. Integrate learnings into unique characterization and test plans for each memory generation.
• Apply understanding of controller design, board design, and DRAM design to define and refine characterization, validation, and POR set methodologies.
• Work closely with memory partners to successfully enable memory into production.
• Work cross-functionally with multiple hardware design and software teams.
• Guide product level decisions for the memory subsystem that span ASIC/VLSI/Board/ATE.

Skills

High-speed DRAM design

Data analysis

Hands-on hardware

Education

Master's degree in Electrical Engineering

Tools

Linux

Python

Job description

NVIDIA is seeking a senior hardware engineer to lead memory subsystem enablement from first silicon to production. You will work with HBM/GDDR, drive test plans, and collaborate across ASIC, board, and software teams.

The role requires 10+ years in high-speed DRAM design and test, plus hands-on hardware and software skills. Equity and comprehensive benefits are offered. Applications close 2026-11-03.