Senior Memory Systems Architect: Performance Modeling Lead

Jobtailor; California (MO); On-site; USD 120,000 - 180,000; Full time

Job summary

Jobtailor is seeking a memory systems architect to drive architecture and micro-architecture for high-performance, power-efficient memories. You’ll model and simulate features, analyze benchmarks, and collaborate across RTL, silicon, and software teams.

The role requires advanced degrees and 3+ years in SoC/memory architecture; proficiency in C/C++, Python, and Verilog; strong communication in a distributed product environment.

Qualifications

• MS/PhD or equivalent experience in relevant field.
• 3+ years in SoC or memory system architecture and performance.
• Deep memory subsystems knowledge: caches, coherence, DDR, memory controllers.
• Strong communication and teamwork in distributed, product-driven environments.
• Exposure to Digital systems and VLSI design, and C/C++ basics.
• Proficiency in C++, Python, and/or Perl; Verilog or SV/UVM are a plus.

Responsibilities

• Develop and refine architecture and micro-architecture for memory systems.
• Model, simulate, and profile performance to guide optimization.
• Analyze benchmarks and workloads to identify tradeoffs in areas of micro-architectural improvements.
• Debug performance and functional issues using models, RTL simulation, and silicon.

Skills

Memory System Architecture

Performance Modeling

C/C++ Programming

Debugging & Profiling

Digital Systems Design

VLSI Design Fundamentals

Education

M.S. or Ph.D. in CS/CE/EE

Tools

Verilog

SV/UVM

Python

Perl

Job description

Jobtailor is seeking a memory systems architect to drive architecture and micro-architecture for high-performance, power-efficient memories. You’ll model and simulate features, analyze benchmarks, and collaborate across RTL, silicon, and software teams.

The role requires advanced degrees and 3+ years in SoC/memory architecture; proficiency in C/C++, Python, and Verilog; strong communication in a distributed product environment.