Senior Memory System Architect

Jobtailor; California (MO); On-site; USD 120,000 - 180,000; Full time

Job summary

Jobtailor is seeking a memory systems architect to drive architecture and micro-architecture for high-performance, power-efficient memories. You’ll model and simulate features, analyze benchmarks, and collaborate across RTL, silicon, and software teams.

The role requires advanced degrees and 3+ years in SoC/memory architecture; proficiency in C/C++, Python, and Verilog; strong communication in a distributed product environment.

Qualifications

• MS/PhD or equivalent experience in relevant field.
• 3+ years in SoC or memory system architecture and performance.
• Deep memory subsystems knowledge: caches, coherence, DDR, memory controllers.
• Strong communication and teamwork in distributed, product-driven environments.
• Exposure to Digital systems and VLSI design, and C/C++ basics.
• Proficiency in C++, Python, and/or Perl; Verilog or SV/UVM are a plus.

Responsibilities

• Develop and refine architecture and micro-architecture for memory systems.
• Model, simulate, and profile performance to guide optimization.
• Analyze benchmarks and workloads to identify tradeoffs in areas of micro-architectural improvements.
• Debug performance and functional issues using models, RTL simulation, and silicon.

Skills

Memory System Architecture

Performance Modeling

C/C++ Programming

Debugging & Profiling

Digital Systems Design

VLSI Design Fundamentals

Education

M.S. or Ph.D. in CS/CE/EE

Tools

Verilog

SV/UVM

Python

Perl

Job description

Driving development of architecture and micro-architecture to improve the state-of-the-art in memory systems optimizing along the axes of performance, power efficiency, complexity, area, effort, and schedule.
Performance modeling and simulation of features to improve memory system performance and efficiency.
Implementing and maintaining detailed and high-level performance models.
Analyzing benchmarks, application workloads, and performance simulation results to identify tradeoffs in areas of micro-architectural optimizations.
Debugging performance and functional issues with high-level models, RTL simulation, and silicon.

Requirements

• M.S. or Ph.D. in CS, CE, or EE or equivalent experience
• 3+ years experience in SoC or memory system architecture and performance
• Deep understanding of memory subsystems – caches and coherence protocols, DDR and memory controller architecture, on-chip interconnects, address translation
• Strong communication and interpersonal skills along with the ability to work in a dynamic, product oriented, distributed team.
• Exposure/coursework related to Digital systems and VLSI design, Computer Architecture, C/C++ programming languages.
• Software development experience with C++, python and/or perl.
• Verilog or SV/UVM are a plus.

Core Competencies

Expertise in memory system architecture and performance optimization, with strong skills in performance modeling, simulation, and debugging. Proficient in C/C++, Python, and Verilog, with a solid understanding of digital systems and VLSI design.

Highest-signal resume keywords

• Memory System Architecture
• Performance Modeling
• C/C++ Programming
• Debugging Skills
• Digital Systems Design

ATS Optimization Keywords

Hard Skills

• Performance Optimization
• Micro-Architecture Development
• Benchmark Analysis
• RTL Simulation
• Verilog
• SV/UVM
• Python
• Perl
• SoC Design
• Memory Controller Architecture

Soft Skills

• Strong Communication Skills
• Interpersonal Skills
• Team Collaboration

Certifications & Qualifications

• M.S. or Ph.D. in CS, CE, or EE

Industry Keywords

• Memory Subsystems
• Caches
• Coherence Protocols
• On-Chip Interconnects
• Address Translation
• VLSI Design
• Computer Architecture