Memory Systems Architect — High-Performance SoC Design

NVIDIA; Austin (TX); On-site; USD 152,000 - 288,000; Full time

Benefits offered by this job

Equity

Benefits

Job summary

NVIDIA is seeking an experienced memory system architect to join our memory system architecture team. You will drive architecture and micro-architecture developments for state-of-the-art memory subsystems in NVIDIA’s SOCs used in AI, autonomous vehicles, robotics, and gaming.

You will model performance, analyze benchmarks, and collaborate with RTL, software, and silicon teams to optimize memory performance, power, and area across diverse platforms.

Qualifications

• MS or PhD in CS/CE/EE (or equivalent experience).
• 3+ years in SoC or memory system architecture and performance.
• Deep memory subsystems knowledge: caches, coherence, DDR, controllers.
• Strong communication in a dynamic, product-focused team.
• coursework in Digital systems, VLSI, Computer Architecture, C/C++.
• Software experience with C++, Python, or Perl; Verilog/SV/UVM a plus.

Responsibilities

• Drive architecture and micro-architecture for memory systems.
• Model and simulate features to improve performance and efficiency.
• Maintain high-level and detailed performance models.
• Analyze benchmarks/workloads to identify tradeoffs.
• Debug performance/functional issues across models, RTL, and silicon.

Skills

SoC architecture

Memory system architecture

Caches & coherence

DDR memory controllers

On-chip interconnects

Address translation

C/C++ programming

Python

Interpersonal communication

VLSI design

Computer Architecture

Digital systems coursework

Education

MS or PhD in CS/CE/EE

Tools

Verilog

SV/UVM

Job description

NVIDIA is seeking an experienced memory system architect to join our memory system architecture team. You will drive architecture and micro-architecture developments for state-of-the-art memory subsystems in NVIDIA’s SOCs used in AI, autonomous vehicles, robotics, and gaming.

You will model performance, analyze benchmarks, and collaborate with RTL, software, and silicon teams to optimize memory performance, power, and area across diverse platforms.