Senior Memory Chip Layout Engineer

TekWissen LLC; Williston (VT); On-site; USD 90,000 - 120,000; Full time

Job summary

A technology solutions provider is looking for a semiconductor memory circuit layout engineer in Williston, Vermont. The role involves developing test sites and product designs, focusing on full chip integration for memory chips, and mastering layout tools like Cadence and Virtuoso. Candidates should possess 5-10 years of experience in memory industry design and be adept at DRC and LVS verification. Strong communication skills and a team-oriented approach are essential.

Qualifications

• Minimum of 5-10 years of memory industry design experience.
• Expertise in full chip integration for memory chips.
• Strong understanding of DRC and LVS verification.

Responsibilities

• Full chip integration for memory chips and Array Diagnostic Monitors.
• Conduct DRC and LVS verification.
• Define signal routing methodology and voltage grids.

Skills

Expert layout of semiconductor logic

Mastery of Cadence and Virtuoso

Ability to run DRC, LVS software

Strong verbal and written communication skills

Team-oriented research environment

Job description

A technology solutions provider is looking for a semiconductor memory circuit layout engineer in Williston, Vermont. The role involves developing test sites and product designs, focusing on full chip integration for memory chips, and mastering layout tools like Cadence and Virtuoso. Candidates should possess 5-10 years of experience in memory industry design and be adept at DRC and LVS verification. Strong communication skills and a team-oriented approach are essential.