Semiconductor Memory circuit layout engineer

TekWissen LLC; Williston (VT); On-site; USD 90,000 - 120,000; Full time

Job summary

A technology solutions provider is looking for a semiconductor memory circuit layout engineer in Williston, Vermont. The role involves developing test sites and product designs, focusing on full chip integration for memory chips, and mastering layout tools like Cadence and Virtuoso. Candidates should possess 5-10 years of experience in memory industry design and be adept at DRC and LVS verification. Strong communication skills and a team-oriented approach are essential.

Qualifications

• Minimum of 5-10 years of memory industry design experience.
• Expertise in full chip integration for memory chips.
• Strong understanding of DRC and LVS verification.

Responsibilities

• Full chip integration for memory chips and Array Diagnostic Monitors.
• Conduct DRC and LVS verification.
• Define signal routing methodology and voltage grids.

Skills

Expert layout of semiconductor logic

Mastery of Cadence and Virtuoso

Ability to run DRC, LVS software

Strong verbal and written communication skills

Team-oriented research environment

Job description

Semiconductor Memory circuit layout engineer

TekWissen provides a unique portfolio of innovative capabilities that seamlessly combines clients insights, strategy, design, software engineering, and systems integration.

The position is for 1 semiconductor memory circuit layout engineer to be involved with the development of test sites and product designs, resident with the design team.

The chosen candidate should have a minimum of 5-10 years of memory industry design experience.

Responsibilities

• Full chip integration for memory chips and Array Diagnostic Monitors (ADM's)
• Full chip DRC and LVS verification
• Definition of full chip signal routing methodology
• Definition of full chip voltage grids and power distribution
• Establishing voltage/reference decoupling cap methodologies that work with signal, power, and fill requirements
• Defining floor plans of entire chips as well as subsystems

Required skills

• Expert layout of semiconductor logic, analogy, and hierarchical systems.
• Mastery of industry standard physical design and layout tools such as Cadence and Virtuoso.
• Ability to run design checking software, e.g. DRC, LVS.
• Strong verbal and written communication skills.
• Must be able to work in close, team oriented research environment.