Senior Manager Test Engineering

OSI Engineering; San Jose (CA); On-site; USD 200,000 - 240,000; Full time

Job summary

A leading semiconductor firm in San Jose is seeking a Senior Manager of Test Engineering. This role involves defining test strategies for next-generation products, managing teams, and collaborating with stakeholders. The ideal candidate will possess a strong background in electrical engineering, DFT methodologies, and experience in high-speed digital products. This is a full-time onsite position offering a salary range of $200,000-$240,000 based on experience.

Qualifications

• 10+ years of experience in a relevant field.
• Deep expertise in DFT methodologies like Scan and ATPG.
• Strong background in DDR and high-speed digital products.

Responsibilities

• Define and drive the ATE roadmap and strategy.
• Lead multiple NPI test engineering teams.
• Manage the full product lifecycle.

Skills

DFT methodologies

Electrical Engineering

Problem-solving mindset

Collaboration skills

Education

B.S./M.S. in Electrical Engineering or equivalent

Tools

Advantest V93k

Job description

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Base pay range

$200,000.00/yr - $240,000.00/yr

Direct message the job poster from OSI Engineering

We are seeking a highly skilled Senior Manager of Test Engineering to join our Operations team. In this leadership role, you will be responsible for shaping and driving the test strategy for next-generation semiconductor products. You will work closely with a team of talented engineers to ensure the performance, reliability, and scalability of solutions that power critical applications in AI, cloud, automotive, and data centers.

This position offers the chance to make a meaningful impact at the forefront of semiconductor innovation. You will be joining a team that values technical excellence, creativity, and collaboration, and your contributions will directly influence the success of products that are shaping the digital future.

Responsibilities:

• Define and drive the ATE roadmap, strategy, and platform selection for current and future products.
• Lead multiple NPI test engineering teams, including hiring, mentoring, and resource planning.
• Manage the full product lifecycle: from design and prototyping to high-volume manufacturing and sustaining support.
• Collaborate cross-functionally with internal teams, customers, and suppliers to ensure seamless execution.
• Optimize yield, test time, and multi-site efficiency to maximize performance and cost-effectiveness.
• Build and maintain infrastructure for new product introductions, including detailed schedules and resource allocation.

Requirements:

• 10+ years of experience with a B.S./M.S. in Electrical Engineering or equivalent.
• Deep expertise in DFT methodologies (Scan, ATPG, JTAG, BIST).
• Hands-on experience with Advantest V93k (Exascale a plus).
• Strong background in DDR and high-speed digital products.
• Experience working with internal test factories and OSATs.
• A proactive, problem-solving mindset and a collaborative spirit.

Location: San Jose, CA, Onsite

Salary Range: $200,000-240,000 (DOE)

Open to candidates willing to relocate.

Seniority level

• Mid-Senior level

Employment type

• Full-time

Job function

• Management and Engineering

Industries

• Semiconductor Manufacturing