Senior Application Engineer - Semiconductor Test

Advantest America; San Jose (CA); On-site; USD 110,000 - 160,000; Full time

Job summary

Advantest America in San Jose, CA is seeking a hands-on Semiconductor Test Application Engineer to bring up, validate, and optimize advanced SoC devices for AI compute and high-performance computing. You will own test programs using SmarTest 8 and V93000, collaborating with silicon, software, and hardware teams to solve complex test challenges on-site.

You will drive pattern workflows, debug hardware interfaces, and build automation in Python/Java/C++ to streamline data analysis and tester

Responsibilities

• Test Program Development: Architect, write, and optimize SoC test programs in modern ATE software environments including SmarTest 8 for AI compute and HPC devices.
• Silicon Bring-Up and Validation: Drive first-silicon bring-up on V93000 testers, debugging interactions between silicon, system behavior, test content, and tester environment.
• Pattern Workflow Engineering: Manage pattern translation, validation, and debugging across DFT and tester workflows using STIL/WGL; support tester bring-up.
• Hardware Co-Design and Debug: Collaborate with PCB and hardware teams to specify, validate, and troubleshoot high-density Device Interface Boards (DIBs).
• Test Time and Automation: Build automation in Python, Java, C++, or similar to analyze logs and STDF data, improve multi-site efficiency, and accelerate learning loops.

Job description

Advantest America develops and supports advanced semiconductor test solutions for next-generation SoC, high-performance computing, RF, and mixed-signal products. We are building a high-caliber application engineering team for engineers who want ownership, customer impact, and hands-on access to leading-edge ATE, silicon, and lab infrastructure as demand for AI compute and inference accelerates.

The Role

This role places you near one of the most important semiconductor buildouts underway: AI compute and inference. You will help bring up, validate, and optimize advanced SoC devices for high-performance computing and large-scale AI infrastructure-working across silicon, software, ATE, and customer programs.

• We are seeking a hands-on Semiconductor Test Application Engineer in San Jose, CA. This role is ideal for an experienced ATE, validation, test development, or system-level debug engineer who wants to solve complex semiconductor test challenges with lab hardware, customer teams, and next-generation Advantest V93000 platforms.
• You will become a key technical owner for Advantest SmarTest 8 and V93000-based SoC test solutions, helping architect, debug, and optimize production-grade test programs for complex devices. Because the work includes hardware bring-up, lab execution, customer collaboration, and fast-moving ramps, the position is based on-site.

What You Will Do

• Test Program Development: Architect, write, debug, and optimize SoC test programs in modern ATE software environments, including Advantest SmarTest 8, for advanced AI compute, inference, and high-performance semiconductor devices.
• Silicon Bring-Up and Validation: Support and help drive first-silicon bring-up on V93000 testers, debugging interactions between silicon, system behavior, test content, and the tester environment.
• Pattern Workflow Engineering: Drive pattern translation, validation, and debug across DFT and tester workflows. Work with STIL, WGL, or comparable pattern sources; support tester bring-up; and collaborate with design and product engineering on emerging virtual test workflows using SmarTest 8 and V93000 environments.
• Hardware Co-Design and Debug: Collaborate with PCB and hardware teams to specify, validate, and troubleshoot high-density Device Interface Boards (DIBs), including signal integrity, power delivery, and tester-to-device interfaces.
• Test Time and Automation: Build automation in Python, Java, C++, or similar languages to analyze logs and STDF data, streamline debug, interface with test platforms, improve multi-site efficiency, and accelerate learning loops.