Senior Manager, Post-Silicon System Integration

NVIDIA; United States; Hybrid; USD 232,000 - 368,000; Full time

Benefits offered by this job

Equity

Flexible time off

Benefits

Job summary

NVIDIA’s Silicon Co-Design Group seeks a Senior Manager to lead System Integration in the US. You’ll drive post-silicon bring-up, validation, and wide-area testing for GPU/SoC/CPU programs, collaborating across architecture, design, firmware, QA, and manufacturing.

You will hire and mentor senior engineers, build repeatable testing capabilities, and shift coverage left to surface issues earlier, ensuring programs hit milestones even when upstream dependencies slip.

Qualifications

• 12+ years of system-level post-silicon bring-up and debug experience.
• 5+ years of leading technical teams with shipped silicon.
• Experience finding critical silicon issues before software is production-ready.
• Experience leading multi-geography teams with talent growth.

Responsibilities

• Plan and execute post-silicon feature integration and wide-area testing across NVIDIA's GPU, SoC, and CPU programs.
• Build wide-area and in-system test as a repeatable capability to surface issues earlier.
• Lead resolution of complex system-level issues (RMAs, HW/SW interactions).
• Develop strategies to keep programs on milestone when dependencies slip (software, firmware, methodology).
• Hire, mentor, and retain senior technical talent; grow IC leadership.
• Partner across architecture, design, DFT, software, firmware, QA, and manufacturing teams.
• Build operational rigor with tracking, debugging forums, and data-driven options for decisions.

Skills

Team leadership

System-level bring-up

Post-silicon validation

Wide-area testing

Executive communication

Education

Bachelor's or Master's in Electrical or Computer Engineering

Tools

DFT knowledge

Hardware/Software debug tooling

Job description

NVIDIA’s Silicon Co-Design Group seeks a Senior Manager to lead System Integration in the US. You’ll drive post-silicon bring-up, validation, and wide-area testing for GPU/SoC/CPU programs, collaborating across architecture, design, firmware, QA, and manufacturing.

You will hire and mentor senior engineers, build repeatable testing capabilities, and shift coverage left to surface issues earlier, ensuring programs hit milestones even when upstream dependencies slip.