Senior Low-Power Wireless SoC Design Engineer

Apple; Irvine (CA); In loco; USD 180.000 - 240.000; Tempo pieno

Descrizione del lavoro

Apple's wireless silicon development team in Irvine, CA seeks a senior engineer to design power management logic for complex wireless SoCs. You will influence energy efficiency across the product stack and work with cross-functional teams to deliver high-performance, low-power solutions.

This role requires deep Verilog proficiency, extensive SoC experience, and strong debug skills, with a track record in post-silicon verification and power analysis.

Competenze

• BS and a minimum of 10 years' relevant industry experience in power/clock/reset management logic design.
• Proficiency in Verilog language.
• Power management logic verification and debug experience.
• Knowledge of CDC, RDC, STA and UPF.
• Proficiency in scripting languages (Shell, Perl or Python).
• Knowledge of common SoC components (CPU, fabric, peripherals).
• Strong problem solving and analytical skills.

Mansioni

• Define SoC power management features to meet product requirements.
• Implement power management logic.
• Work with XF teams to verify power management logic.
• Support Power team on power analysis and post-silicon correlation efforts.
• Post silicon bring up and debug support.

Conoscenze

Power management

Verilog

Shell/Python

SoC components

CDC/RDC/STA/UPF

Formazione

BS in Electrical Engineering or related field

Descrizione del lavoro

Apple's wireless silicon development team in Irvine, CA seeks a senior engineer to design power management logic for complex wireless SoCs. You will influence energy efficiency across the product stack and work with cross-functional teams to deliver high-performance, low-power solutions.

This role requires deep Verilog proficiency, extensive SoC experience, and strong debug skills, with a track record in post-silicon verification and power analysis.