Senior AI Data Center Interconnect Architect

BizLink Group; Fremont (CA); On-site; USD 180,000 - 280,000; Full time

Job summary

BizLink Group in Fremont, CA is seeking a Senior High-Speed Interconnect Architect to define the architecture for advanced AI servers and rack systems, including backplanes, co-packaged copper, OSFP, PCIe, and OSFP-X. You will balance performance, signal integrity, power, and manufacturability.

Collaborate with hardware, system, packaging, and software teams; engage with standards bodies such as PCI-SIG, IEEE, and CXL; contribute to roadmaps and technical specifications for scalable interconnect

Qualifications

• Minimum of 10 years of professional experience in high-speed interconnect architecture, signal integrity, or system design for AI/HPC platforms.
• Extensive expertise in high-speed protocols (NVLINK, UALINK, PCIe, CXL, Ethernet, InfiniBand, OSFP, OSFP-X) and advanced connector/cabling technologies.
• Comprehensive knowledge of signal integrity, power integrity, PCB/package/system design, and relevant simulation tools.
• Proven experience in participating in or influencing industry standards development.

Responsibilities

• Architectural Design and Optimization of high-speed interconnect solutions for AI/ML and HPC platforms.
• Technology Assessment of interconnect standards and future scalability.
• Signal and Power Integrity collaboration with engineers to ensure robust data transmission.
• Interdepartmental collaboration with hardware, system, packaging, and software teams.
• Industry Standards Participation in bodies like OCP, PCI-SIG, and CXL Consortium.
• Client and Partner Liaison to align requirements and foster collaboration.
• Technical Documentation and roadmapping for high-speed interconnects.

Skills

10+ years exp

Electrical Eng

Signal Integrity

Power Integrity

PCB/Package Design

Cross-functional Leadership

Standards Bodies

Education

Electrical/Computer Engineering degree

Job description

BizLink Group in Fremont, CA is seeking a Senior High-Speed Interconnect Architect to define the architecture for advanced AI servers and rack systems, including backplanes, co-packaged copper, OSFP, PCIe, and OSFP-X. You will balance performance, signal integrity, power, and manufacturability.

Collaborate with hardware, system, packaging, and software teams; engage with standards bodies such as PCI-SIG, IEEE, and CXL; contribute to roadmaps and technical specifications for scalable interconnect