Senior Lead Data Converter IC Designer (ADC/DAC, FinFET)

Encore Semi, Inc.; Chandler (AZ); À distance; USD 150 000 - 180 000; Plein temps

Avantages offerts par ce poste

15 days PTO per year

10 paid holidays per year

Medical benefits (80% premiums)

Dental & Vision 50%

Life Insurance

Tuition reimbursement

Résumé du poste

Encore Semi, Inc. seeks an experienced Senior/Lead Data Converter IC Design Engineer (FinFET) to architect and tape out high-speed ADC/DACs in advanced nodes.

You will own the full design cycle from system architecture to post-silicon validation for HPC and AI hardware. Responsibilities include designing multi-GS/s ADC/DAC architectures, transistor-level circuits, digital calibration, layout supervision, and post-silicon verification.

Qualifications

• MS or PhD in Electrical Engineering or related field.
• 10+ years of hands-on high-speed data converter design and successful silicon tape-outs.
• FinFET Expertise: 3nm/5nm/7nm experience.
• Strong command of FinFET‑specific design constraints (fin quantization, degraded gm/gds, 3D RC extraction).
• EDA Tools: Cadence Virtuoso, Spectre/PrimeSim, and Calibre PEX/Quantus.

Responsabilités

• Architect and design multi-GS/s ADC/DAC architectures (Time-Interleaved SAR, Pipeline, Flash, or RF-DACs).
• Deliver transistor-level circuits (track-and-hold, comparators, low-jitter clock paths, bias networks) in 7nm–3nm FinFET processes.
• Implement background/foreground digital calibration for offset, gain, timing skew, and linearity.
• Supervise layout to mitigate layout-dependent effects (LDE), parasitics, electromigration, and self-heating.
• Lead post-silicon lab bring-up, bench testing, and model-to-hardware correlation.

Connaissances

High-speed data converter design

ADC/DAC architecture

FinFET knowledge

Formation

MS or PhD in Electrical Engineering

Outils

Cadence Virtuoso

Spectre/PrimeSim

Calibre PEX/Quantus

Description du poste

Encore Semi, Inc. seeks an experienced Senior/Lead Data Converter IC Design Engineer (FinFET) to architect and tape out high-speed ADC/DACs in advanced nodes.

You will own the full design cycle from system architecture to post-silicon validation for HPC and AI hardware. Responsibilities include designing multi-GS/s ADC/DAC architectures, transistor-level circuits, digital calibration, layout supervision, and post-silicon verification.