Senior Data Converter IC Design Lead (FinFET) Remote

Encore Semi Llc; Austin (TX); Remote; USD 150,000 - 180,000; Full time

Benefits offered by this job

Paid PTO

Holidays

Medical benefits

Dental/vision

Voluntary benefits

EAP

401k

Life/AD&D

Long-term disability

Tuition reimbursement

Job summary

Encore Semi, Inc. is seeking an experienced Senior/Lead Data Converter IC Design Engineer to architect and tape out high‑speed ADC/DAC architectures in FinFET nodes from 7nm to 3nm.

You will own the full design cycle from system architecture to post‑silicon validation for HPC, AI and communications hardware. You will implement background/foreground digital calibration and supervise layout to mitigate LDE and parasitics, leading post‑silicon lab bring‑up and model‑to‑hardware correlation.

Qualifications

• MS or PhD in Electrical Engineering or related field.
• 10+ years of hands-on high-speed data converter design and tape-outs.
• FinFET expertise in 3nm/5nm/7nm nodes.
• Strong FinFET design constraints knowledge (gm/gds, 3D RC extraction).

Responsibilities

• Architect and design multi-GS/s ADC/DAC architectures.
• Deliver transistor-level circuits in 7nm–3nm FinFET processes.
• Implement background/foreground digital calibration for offset, gain, timing skew, and linearity.
• Supervise layout to mitigate layout-dependent effects (LDE), parasitics, electromigration, and self-heating.
• Lead post-silicon lab bring-up and model-to-hardware correlation.

Skills

High-speed data converter design

Tape-out experience

FinFET process design

Low-noise, high-precision analog

Digital calibration knowledge

Education

MS/PhD in Electrical Engineering

Tools

Cadence Virtuoso

Spectre/PrimeSim

Calibre PEX/Quantus

Job description

Encore Semi, Inc. is seeking an experienced Senior/Lead Data Converter IC Design Engineer to architect and tape out high‑speed ADC/DAC architectures in FinFET nodes from 7nm to 3nm.

You will own the full design cycle from system architecture to post‑silicon validation for HPC, AI and communications hardware. You will implement background/foreground digital calibration and supervise layout to mitigate LDE and parasitics, leading post‑silicon lab bring‑up and model‑to‑hardware correlation.