Senior High-Speed ADC/DAC IC Designer — 7nm FinFET

Encore Semi, Inc.; Raleigh (NC); Remote; USD 150,000 - 180,000; Full time

Benefits offered by this job

15 days PTO per year

10 paid Holidays per year

Medical benefits 80% premiums

Dental & Vision 50% premiums

Life Insurance

401k - Traditional & Roth

EAP

Tuition reimbursement

Long-Term Disability

Job summary

Encore Semi, Inc. seeks an experienced Analog/Mixed-Signal IC Design Engineer to architect and tape out high-speed ADC/DACs in 7nm down to 3nm FinFET processes.

You will own the full cycle from system architecture to post-silicon validation for HPC, AI, and communications hardware. You will design transistor-level circuits, implement digital calibration, and supervise layout to mitigate LDE and parasitics, while leading post-silicon bring-up and model-to-hardware correlation.

Qualifications

• MS or PhD in Electrical Engineering or related field.
• 10+ years in high-speed data converter design and silicon tape-outs.
• Experience with FinFET nodes (3nm–7nm).
• Deep knowledge of FinFET design constraints and 3D RC extraction.
• Proficiency with Cadence Virtuoso, Spectre/PrimeSim, and Calibre tools.

Responsibilities

• Architect and design multi-GS/s ADC/DAC architectures (Time-Interleaved SAR, Pipeline, Flash, RF-DACs).
• Deliver transistor-level circuits (track-and-hold, comparators, low-jitter clocks, bias networks).
• Implement background/foreground digital calibration for offset, gain, timing skew, and linearity.
• Supervise layout to mitigate LDE, parasitics, electromigration, and self-heating.
• Lead post-silicon lab bring-up, bench testing, and model-to-hardware correlation.

Skills

Analog IC design

High-speed data converters

Mixed-signal design

FinFET design constraints

Layout-aware design

Education

M.S. in Electrical Engineering

Ph.D. in Electrical Engineering

Tools

Cadence Virtuoso

Spectre/PrimeSim

Calibre PEX/Quantus

Job description

Encore Semi, Inc. seeks an experienced Analog/Mixed-Signal IC Design Engineer to architect and tape out high-speed ADC/DACs in 7nm down to 3nm FinFET processes.

You will own the full cycle from system architecture to post-silicon validation for HPC, AI, and communications hardware. You will design transistor-level circuits, implement digital calibration, and supervise layout to mitigate LDE and parasitics, while leading post-silicon bring-up and model-to-hardware correlation.