Senior Data Converter IC Design Engineer (FinFET, Remote)

Encore Semi Llc; Chandler (AZ); À distance; USD 150 000 - 180 000; Plein temps

Avantages offerts par ce poste

15 days PTO per year

10 paid holidays per year

Medical benefits; 80% premiums covered

Dental & Vision; 50% premiums covered

Life Insurance & LTD

Tuition reimbursement

Résumé du poste

Encore Semi, Inc. in the United States seeks an experienced Senior/Lead Data Converter IC Design Engineer to architect and tape out high-speed ADC/DACs in FinFET nodes from 7nm down to 3nm.

You will own the full design cycle—from system architecture to post-silicon validation—for HPC, AI, and communications hardware. Responsibilities include leading multi-GS/s converter architectures, transistor-level design, calibration, layout supervision, and lab bring-up.

Qualifications

• MS or PhD in Electrical Engineering or related field.
• 10+ years of hands-on high-speed data converter design and successful silicon tape-outs.
• FinFET Expertise: advanced nodes (3nm, 5nm, or 7nm).

Responsabilités

• Architect and design multi-GS/s ADC/DAC architectures (Time-Interleaved SAR, Pipeline, Flash, or RF-DACs).
• Deliver transistor-level circuits (track-and-hold, comparators, low-jitter clock paths, bias networks) in 7nm–3nm FinFET processes.
• Implement background/foreground digital calibration for offset, gain, timing skew, and linearity.
• Supervise layout to mitigate layout-dependent effects (LDE), parasitics, electromigration, and self-heating.
• Lead post-silicon lab bring-up, bench testing, and model-to-hardware correlation.

Connaissances

Analog/Mixed-Signal IC design

High-speed data converters

System architecture

Post-silicon validation

Formation

MS/PhD in Electrical Engineering

Outils

Cadence Virtuoso

Spectre/PrimeSim

Calibre PEX/Quantus

Description du poste

Encore Semi, Inc. in the United States seeks an experienced Senior/Lead Data Converter IC Design Engineer to architect and tape out high-speed ADC/DACs in FinFET nodes from 7nm down to 3nm.

You will own the full design cycle—from system architecture to post-silicon validation—for HPC, AI, and communications hardware. Responsibilities include leading multi-GS/s converter architectures, transistor-level design, calibration, layout supervision, and lab bring-up.