Physical Design Engineer II (IC)

Arrow Electronics; San Jose (CA); On-site; USD 87,400 - 165,000; Full time

Job summary

Arrow Electronics is seeking a Physical Design Engineer II to drive ASIC partition implementation, including synthesis, place-and-route, and timing convergence. You will collaborate with architects, RTL designers, and DFT engineers to resolve issues and ensure clean signoffs.

Strong PD flow expertise and TCL scripting are highly valued. The role requires 7+ years in physical design, proficiency with Innovus/Tempus/Quantus, and experience in SoC design and sub-7nm processes.

Qualifications

• Bachelor's degree or equivalent practical experience in a related technical field.
• 7+ years hands-on experience in physical design and implementation (synthesis, PnR, timing convergence, physical verification).
• Proficiency with EDA tools (Innovus, Tempus, Quantus) and strong knowledge of PD flows and methodologies.

Responsibilities

• Execute synthesis, PnR, and STA for assigned ASIC partitions within schedules and goals.
• Collaborate with architects, RTL, and DFT teams to resolve issues across blocks.
• Close EM/IR, drive LEC and physical verification signoff with methodology owners.
• Identify and address physical design challenges, enabling efficient iteration and convergence.

Skills

Physical design

Low-power design techniques

SoC experience

TCL scripting

Education

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field

Tools

Innovus

Tempus

Quantus

Job description

## Physical Design Engineer II (IC)Applylocations: US-CA-San Jose, Californiatime type: Full timeposted on: Posted Yesterdayjob requisition id: R246447# **Position:**Physical Design Engineer II (IC)# **Job Description:****Job Responsibilities:*** **Execute synthesis, PNR, and STA for assigned partitions of ASIC chip adhering to strict schedules and design goals.*** **Work closely with architects, RTL designers, and DFT engineers to resolve implementation and signoff issues across your blocks.*** **Help close EM/IR, drive LEC and physical verification signoff for your partitions in coordination with methodology owners.*** **Partner with the design team to proactively identify and address potential physical design challenges, enabling efficient iteration and convergence.*** **Contribute to the refinement of other implementation and physical design methodologies, encompassing synthesis, place and route (PnR), electromigration and IR (EMIR), power delivery network (PDN), and logical equivalence checking (LEC).*** **Troubleshoot flow issues and collaborate with EDA vendors to resolve them as needed.****Minimum Qualifications:*** **Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field, or equivalent practical experience.*** **7+ years of hands-on experience in physical design and implementation, encompassing synthesis, PnR, timing convergence and physical verification.*** **Proficiency in utilizing Electronic Design Automation (EDA) tools such as Innovus, Tempus, and Quantus, as well as a deep understanding of physical design flows and methodologies.********Preferred Qualifications:*** **7+ years of experience in physical design roles and related activities.*** **Proven ability to adhere to tight schedules and implement low-power design techniques.*** **Experience in System-on-Chip (SoC) design and implementation.*** **Expertise in sub-7nm node technologies.*** **Familiarity with industry-standard EDA tools and their capabilities.*** **Strong scripting skills in TCL to develop custom flows and methodologies on standard EDA tools from Cadence/Synopsys.**# **Annual Hiring Range/Hourly Rate:**$87,400.00 - $165,000.00Actual compensation offer to candidate may vary from posted hiring range based upon geographic location, work experience, education, and/or skill level. The pay ratio between base pay and target incentive (if applicable) will be finalized at offer. # **Location:**US-CA-San Jose, California (eInfochips)# **Time Type:**Full time# **Job Category:**Engineering Services# **EEO Statement:**Arrow is an equal opportunity employer. All applicants will be considered for employment without attention to race, color, religion, gender, age, sexual orientation, gender identity, national origin, veteran or disability status. (Arrow EEO/AAP policy)*All Arrow job postings are for existing job vacancies*. *We anticipate this requisition will be open for a minimum of five days, though it may be open for a longer period of time. We encourage your prompt application.**In any materials you submit, you may redact or remove age-identifying information such as age, date of birth, or dates of school attendance or graduation. You will not be penalized for redacting or removing this information.*