Senior IC Package Design Engineer for Space & RF

United States Digital Space LLC; Austin (CA); On-site; USD 165,000 - 260,000; Full time

Benefits offered by this job

Stock options

Medical, dental, vision coverage

401(k) plan

Paid vacation

Holidays and sick leave

Job summary

United States Digital Space LLC in Austin, Texas is seeking a Sr. IC Package Design Engineer (Silicon Engineering) to lead packaging for in-house ASICs and RFICs for digital beam formers and modems.

You will own package selection, layout, verification, and tapeout, collaborating with cross-functional teams across the company. The role requires 5+ years in IC package design, hands-on experience with SI/PI, RF, and substrate design for high-speed die; familiarity with Cadence APD+/SIPor similar

Qualifications

• Bachelor's degree in electrical/ computer engineering or physics.
• 5+ years of experience with IC package design.
• Experience with Co-packaged Optics (CPO) is a plus.
• Strong SI/PI and RF/substrate design fundamentals.

Responsibilities

• Own and drive advanced package selection and BGA configuration.
• Manage package/SIP layout, verification and tapeout.
• Coordinate with cross-functional groups on packaging feasibility and design.
• Optimize silicon floor plan, bump and package pinout.
• Simulate and optimize signal/power integrity and RF performance.

Skills

IC package design

Signal integrity

Power integrity

RF package design

EM simulation

SI/PI analysis

Education

Bachelor's degree in electrical engineering, computer engineering, or physics

Tools

Cadence APD+/SIPor

SIWave

HFSS

ADS

Job description

United States Digital Space LLC in Austin, Texas is seeking a Sr. IC Package Design Engineer (Silicon Engineering) to lead packaging for in-house ASICs and RFICs for digital beam formers and modems.

You will own package selection, layout, verification, and tapeout, collaborating with cross-functional teams across the company. The role requires 5+ years in IC package design, hands-on experience with SI/PI, RF, and substrate design for high-speed die; familiarity with Cadence APD+/SIPor similar