I/O Architect

Eliyan; United States; On-site; USD 180,000 - 280,000; Full time

Benefits offered by this job

Excellent benefits

Job summary

Eliyan is seeking an experienced NuLink PHY IO Architect to define subsystems, drive RTL-to-GDSII ASIC development, and lead cross-functional teams in a fast-paced startup environment. You will shape architecture, oversee design and validation, and push for best-in-class performance, power, and manufacturability.

You will mentor engineers, develop advanced design flows, and ensure protocol interoperability across PCIe, UCIe, DDR, and AMBA domains while collaborating with customers and marketing

Qualifications

• 15+ years of experience in ASIC architecture and leadership
• Strong knowledge of two or more connectivity protocols such as PCIe, UCIe, DDR, AMBA
• Expertise in architecture definition, chip micro-architecture and protocol implementation
• Adept at clocking, floorplanning guidelines, and power-aware design
• Proven track record leading teams through tapeouts and delivering manufacturable IP

Responsibilities

• Define NuLink PHY subsystems and hierarchical protocol bridges (PCIe, AXI4, CHI, CXL, DDR)
• Oversee architecture, design, and validation across RTL to GDSII
• Develop and improve design flows and methodologies for on-time delivery
• Create architecture specs with clear integration guidelines for cross-functional teams
• Mentor engineers on protocol implementation, timing, and physical constraints
• Collaborate with ASIC, firmware, and post-silicon teams to support customer integrations
• Ensure compliance with UCIe, PCIe, CXL, AMBA AXI/APB, and DDR standards

Skills

ASIC Architecture

RTL Design

Protocol Design

Scripting & Automation

Clocking & Floorplanning

Education

B.S. or M.S. in Electrical/Computer Engineering

Tools

RTL-to-GDSII flows

Job description

• Join the leading chiplet startup
• As an Eliyan NuLink PHY IO Architect, you will be working at a fast-paced early-stage startup creating technologies that fuel tomorrow's chiplet based systems with best-in-class power, area, manufacturability, and design flexibility
• You will drive the definition and development of cutting-edge ASICs from RTL to GDSII
• You will work with a cross-functional team of industry experts that operate from first principles, innovate, and push the envelope to create high-volume and high-performance manufacturable products
• In this role, you will own the architecture, oversee design and validation, and be a focal point for customer and marketing team interactions
• You will also focus on developing and improving design flows and methodologies to ensure high-quality, on-time delivery
• We offer a fun work environment with excellent benefits
• ONSITE M-F
• Architecture: Define NuLink PHY subsystems (physical and logical/link layers) and hierarchical modular protocol bridges between PCIe, AXI4, APB, CHI, CXL (.io/.cache/.mem), DDR to name a few. Definition of a firmware first based hardware architecture approach
• Protocol Design: Design protocol conversion layers with transaction ordering, credit-based flow control, QoS, address translation, coherency management, and memory semantics across protocol domains
• Performance Evaluation and Optimization: Model and tune PHY data path, link protocols, and CDC architectures for protocol efficiency, bandwidth, latency, power, and signal integrity. Conduct technical evaluation and benchmark analysis against internal and external IPs
• Collaboration: Partner with ASIC, firmware, and post-silicon teams. Support customer integration for compute-to-memory (CXL/DDR), processor interconnect (AXI/PCIe), and control plane (APB). Create clear and comprehensive architecture specifications with foolproof integration guidelines
• Validation: Review characterization plans for PLL, VCO, ATB, and link training. Create protocol testbenches validating transaction handling, latency, throughput, and compliance
• Compliance: Ensure UCIe, PCIe, CXL, AMBA AXI/APB, and DDR specification compliance. Define interoperability requirements and protocol error handling. Be part of industry standards bodies and work groups to keep Eliyan's product implementations up to date with the latest versions of the standards
• Leadership: Mentor engineers on protocol implementation, timing constraints, and hierarchical design. Effectively collaborate with industry technologists, business leaders and ability to network seamlessly with industry peers to influence stakeholders

Expertise in multiple areas of architecture definition, chip micro-architecture, protocol definition and implementation8+ years' of experienceStrong scripting and automation skillsStrong knowledge of two or more of the following connectivity protocols - PCIe, UCIe, UALink, Ethernet, DDR, AMBA Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field15+ years of experience in ASIC architecture with strong bias for practical logic design and influence of physical implementation, with a proven track record of leading teams through successful tapeoutsPerformance modeling of hardware implementations with high level languages like C, C++ or SystemCAdept at clocking and floorplan guidelines for PHY implementationExceptional problem-solving skillsExtremely knowledgeable on RTL-to-GDSII flows, limitations, and flexibilities to improve productivity and power aware designs