Senior High-Speed SERDES Standards Architect

NOKIA

San Jose (CA)

On-site

USD 180,000 - 230,000

Full time

11 days ago

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Job summary

Nokia seeks a senior standards engineer to shape high‑speed electrical interfaces and SERDES specifications for 400 Gb/s per lane and beyond. You will collaborate with Product, silicon and hardware teams to define objectives and draft baseline standard text for IEEE 802.3 and OIF.

You will analyze links and channels, evaluate PAM4 and modulation options, and advocate technical positions to customers, suppliers and industry bodies while coordinating across time zones and partners.

Qualifications

Bachelor's degree in electrical engineering, computer engineering, applied physics or a closely related field is required; a master's degree or PhD is preferred.
Substantial hands‑on experience in high‑speed SERDES, electrical PHY or mixed‑signal interface design, architecture, modelling, validation or product development.
Deep understanding of high‑speed serial‑link fundamentals, including transmitter and receiver architectures, clocking and CDR, jitter, phase noise, noise coupling, channel impairments, equalisation and link training.
Expertise with PAM4 signalling and a strong foundation in modulation, coding, BER, error distributions and the interaction between electrical link performance and FEC.
Experience with high‑speed interface applications such as die‑to‑die, chip‑to‑chip, chip‑to‑module, backplane, copper cable or active electrical cable links.
Working knowledge of Ethernet PHY architecture and terminology, including PCS, FEC, PMA, AUI, PMD, lane mapping and multi‑lane aggregation.
Practical experience with channel and link analysis tools and methods, such as S‑parameters, eye and bathtub analysis, statistical simulation, IBIS‑AMI, COM, MATLAB, Python or equivalent engineering environments.
Understanding of packaging, connector, PCB, cable and module constraints at very high signalling rates, including their impact on signal integrity, power integrity and test methodology.
Experience developing specifications, compliance methods, test fixtures or interoperability plans. Familiarity with BERTs, oscilloscopes, VNAs and high‑speed electrical measurements is highly desirable.
Experience participating in IEEE 802.3, OIF or another consensus‑based standards organisation is strongly preferred. Demonstrated contribution authorship, technical editing or leadership is an advantage.
Excellent written and verbal communication skills, with the ability to explain complex engineering trade‑offs to specialists, executives, customers and partners.

Responsibilities

Provide deep high‑speed electrical I/O and SERDES expertise to shape 400 Gb/s‑per‑lane and higher standards in IEEE 802.3 and OIF.
Work with product line managers, silicon and hardware architects to identify standardisation objectives for next-gen high-speed interfaces.
Develop and regularly review Nokia standardisation strategies for chip‑to‑chip, chip‑to‑module, backplane and copper‑cable interfaces.
Create, analyse and advocate technical contributions for IEEE 802.3 and OIF projects; build consensus with ecosystem partners and customers.
Perform link and system analysis to support standards decisions, including jitter, loss limits, crosstalk and interop trade‑offs.
Evaluate modulation and architecture options for 400 Gb/s per lane, considering power, latency and manufacturability.
Translate requirements into rigorous standards proposals, baseline text and responses to comments.
Monitor competing proposals and develop constructive technical alternatives when required.
Participate in IEEE 802.3/WG and OIF activities and relevant industry alliances.
Provide concise internal reports on standards progress and technical risks for R&D and leadership.