Senior Hardware Design & Signal Integrity Engineer

Arista; Santa Clara (CA); On-site; USD 140,000 - 200,000; Full time

Benefits offered by this job

Snack events

Wellness programs

Employee engagement & volunteering

Job summary

Arista Networks in Santa Clara, CA, seeks a seasoned Hardware Engineer to design and debug high‑speed networking hardware. You will tackle complex issues in DDR/PCIe, work across CPU/ASIC, power and SI, and deliver robust fixes with minimal field impact.

You will collaborate with software, product management, and manufacturing teams, perform root cause analysis, read logs, and craft solutions while contributing to test plans and new hardware validation.

Qualifications

• 5+ years of hardware engineering experience.
• Experience debugging networking hardware and delivering root cause fixes.
• Experience with high speed interfaces (DDR, PCIe) and low speed signals (I2C, SPI).
• Experience with multi‑phase DC/DC for high current loads.

Responsibilities

• Debug production system problems and deliver solutions.
• Identify test escapes and develop new tests with design validation.
• Write and present root cause analyses to executives and customers.

Skills

High-speed interfaces

FPGA design

Signal integrity

Debugging

Root cause analysis

PCIe

DDR

Education

BSEE or MSEE

Tools

PCIe analyzers

TDRs

VNA

Oscilloscope

Job description

Arista Networks in Santa Clara, CA, seeks a seasoned Hardware Engineer to design and debug high‑speed networking hardware. You will tackle complex issues in DDR/PCIe, work across CPU/ASIC, power and SI, and deliver robust fixes with minimal field impact.

You will collaborate with software, product management, and manufacturing teams, perform root cause analysis, read logs, and craft solutions while contributing to test plans and new hardware validation.