Hardware Design Integrity Engineer

Arista; Santa Clara (CA); On-site; USD 140,000 - 200,000; Full time

Benefits offered by this job

Snack events

Wellness programs

Employee engagement & volunteering

Job summary

Arista Networks in Santa Clara, CA, seeks a seasoned Hardware Engineer to design and debug high‑speed networking hardware. You will tackle complex issues in DDR/PCIe, work across CPU/ASIC, power and SI, and deliver robust fixes with minimal field impact.

You will collaborate with software, product management, and manufacturing teams, perform root cause analysis, read logs, and craft solutions while contributing to test plans and new hardware validation.

Qualifications

• 5+ years of hardware engineering experience.
• Experience debugging networking hardware and delivering root cause fixes.
• Experience with high speed interfaces (DDR, PCIe) and low speed signals (I2C, SPI).
• Experience with multi‑phase DC/DC for high current loads.

Responsibilities

• Debug production system problems and deliver solutions.
• Identify test escapes and develop new tests with design validation.
• Write and present root cause analyses to executives and customers.

Skills

High-speed interfaces

FPGA design

Signal integrity

Debugging

Root cause analysis

PCIe

DDR

Education

BSEE or MSEE

Tools

PCIe analyzers

TDRs

VNA

Oscilloscope

Job description

• Working closely with cross-functional teams including software, product management, and manufacturing, our engineers innovate on system architectures, high-speed PCB designs, and signal integrity to deliver state‑of‑the‑art products that drive network performance and reliability
• Our Hardware Engineering team is at the forefront of developing high-speed networking and Ethernet products used in Enterprise campuses, hyperscaler datacenters and bleeding edge AI clusters
• With this comes complex, oftentimes cross-platform issues requiring engineers passionate about debugging and delivering root cause analysis and fixes to the design team, executives, and customers
• Candidates for this position would be responsible for debugging production system problems and delivering solutions
• Deep dive into various aspects of any existing hardware design - CPU/ASIC, power, SI, clocking, PCIE, optics, fab, components
• Work closely with sw & customer teams on high pressure escalations from the field, including reading logs, identifying the bug, determining the best fix with minimal interruption to the field, delivering the final solution, determining if any other systems are susceptible, and implementing measures to prevent the issue from occurring again
• Writing scripts to look for specific information in the logs or to capture information in live debug sessions
• Work closely with the hw design team, but also be able to make firmware, schematic, BOM, fab changes as needed
• Lab measurements and debug
• Work closely with component, FA, ODM teams to identify component level or third party RCAs and fixes needed
• Identify test escapes. Work with the design validation team to examine current test limitations and develop new tests
• Write and present root cause analysis for executives and customers

Benefits

• Regular ”Snack Bash” Social Events with food and drinks!
• Biweekly Wellness webinars plus regular Wellness Week events focused on physical, mental, spiritual and financial wellness as well as career development and social activities
• Arista Gives Back: Employee Engagement Giving Drives and Volunteer events
• Medical, Dental & Vision Plan Coverage
• Life Insurance, AD&D, STD & LTD
• Flex Spending Accounts
• Employee Assistance Programs
• PTO & Paid holidays
• 401k Plan
• On-site Gym & Showers
• Secured Bike Lockers
• Secured Bike Lockers
• Flexible hours
• Employee Assistance Benefits that include mental health and backup child and elder care support
• Discounted lunches through WeBox for HQ employees
• Family planning benefits

Experience with design and debug of high speed interfaces (DDR, PCIe) as well as low speed signals (I2C, SPI)Experience debugging and validating multi-phase DC/DC’s for high current, high transient loadsFamiliarity with signal integrity and power integrity concepts and tools, such as: impedance, PDN’s, Bode plots, PCIE analyzers, TDR’s, VNA’s5+ years of relevant experience in hardware engineeringExperience debugging Networking HardwareBSEE or MSEEFPGA design using VerilogExperience with proper design of 20+ layer count boards featuring 50G+ signals