Senior Hardware Design Engineer for AI Acceleration Boards

Unigen Corporation; Fremont (CA); On-site; USD 120,000 - 180,000; Full time

Job summary

Unigen Corporation in Newark, California is seeking a Senior Hardware Design Engineer to lead high-density PCB design for AI accelerator platforms. You will own schematic capture, layout, and validation across the full design lifecycle.

The role requires expertise in high-speed interfaces (DDR4/5, PCIe Gen5/6), power integrity, and thermal considerations, with hands-on lab bring-up and debugging across hardware and firmware.

Qualifications

• Bachelor’s degree in electrical engineering or related field required.
• 1) 10+ years designing high-speed digital/analog circuitry on complex high-density PCBs.
• 2) 5+ years in design of high-density boards with fine pitch components and high-density connectors, with DDR4/5 and PCIe Gen5/6 experience.
• 3) System-level validation in complex hardware/software environments.
• 4) Strong debugging across system, firmware and hardware domains.
• 5) Proficiency in Python or C and understanding EVT/DVT methodologies.

Responsibilities

• Architect and implement high-density PCB designs for AI accelerator carrier cards and host boards.
• Own full-lifecycle schematic capture and design optimization for complex boards.
• Implement and optimize high-speed interfaces (DDR4/5, PCIe Gen5/6).
• Define robust PDN for massive transient currents and thermal management.
• Lead lab bring-up, debugging, and validation of pre-production hardware.
• Drive root-cause analyses and reliability improvements for hyperscale deployments.

Skills

High-speed design

PCB design

Hardware validation

Scripting (Python/C)

Debugging

Team mentoring

Education

Bachelor’s degree in electrical engineering or related field

Tools

Oscilloscopes

Logic analyzers

Protocol analyzers

Job description

Unigen Corporation in Newark, California is seeking a Senior Hardware Design Engineer to lead high-density PCB design for AI accelerator platforms. You will own schematic capture, layout, and validation across the full design lifecycle.

The role requires expertise in high-speed interfaces (DDR4/5, PCIe Gen5/6), power integrity, and thermal considerations, with hands-on lab bring-up and debugging across hardware and firmware.