Senior High-Speed PCB Design Engineer - Lab Ownership

GCS Recruitment; Redmond (WA); Sur place; USD 150 000 - 210 000; Plein temps

Résumé du poste

GCS Recruitment Specialists seeks a senior hardware engineer responsible for end-to-end board design in a phased-array signal chain. You will own schematic capture, component selection, and 20+ layer board layouts, coordinating with lab bring-up and validation cycles.

This role demands bench-centric debugging and hands-on lab leadership. You will architect power delivery for boards with hundreds of high-performance chips, and you will design and validate SerDes-class interfaces (PCIe, JESD204,

Qualifications

• 8+ years of board-level design ownership with verifiable prototype-to-production delivery.
• Expertise in high-speed digital interfaces like SerDes, PCIe, JESD204 and DDR.
• Experience architecting power delivery for dense, high-power boards.
• Proven lab fluency: bring-up, bench debugging, and root-cause analysis with instruments.
• Understanding of controlled impedance, length matching, and stackup design.

Responsabilités

• Own design of 20+ layer boards from schematic capture to layout ownership.
• Architect power delivery for multi-chip boards and validate performance.
• Design and validate multi-gigabit interfaces with SI/PI discipline.
• Bring up newly fabricated boards, perform first power-on checks, and debug to root cause.
• Run validation campaigns and feed findings into next revisions.
• Select components with reliability, thermal, vibration, and radiation considerations.

Connaissances

Board-level design ownership

High-speed digital design

SerDes/PCIe/JESD204

Power-architecture for dense boards

Lab bring-up & debugging

Signal integrity practices

Outils

Oscilloscopes

Analyzers

Description du poste

THE ROLE

You will own complex, high-speed board design in the phased-array signal chain - and see your designs through the lab. The team runs design and validation in parallel: while one board revision is being validated at the bench, the next is in design. You'll design boards (schematic capture, component selection, layout ownership), personally bring up newly fabricated hardware, debug to root cause, and feed findings into the next revision. This is a design-first seat with real lab ownership - not a test role, and not a documentation role.

WHAT YOU'LL DO

• Design high-complexity, high-speed digital boards: schematic capture, component selection, and layout ownership on 20+ layer, thousands-of-components designs built around custom silicon.

• Architect power delivery for boards carrying hundreds of high-performance chips - rail generation, sequencing, budgeting, and protection.

• Design and validate multi-gigabit interfaces (SerDes-class links, JESD204, PCIe, DDR) with disciplined signal- and power-integrity practice.

• Bring up newly fabricated boards in the lab: first power-on, section-by-section checkout, root-cause debug with oscilloscopes and high-speed instrumentation.

• Run validation campaigns proving designs meet requirements, and feed every finding into the next board revision.

• Select components with reliability, thermal, vibration, and radiation considerations in partnership with specialist review teams.

REQUIRED EXPERIENCE

• 8+ years of board-level design ownership - complex boards you can point to and say "mine": schematic, component selection, and layout.

• High-speed digital design: SerDes, JESD204, PCIe, and/or DDR, with hands-on signal-integrity practice (controlled impedance, length matching, stackup design).

• Power-architecture design for dense, high-power boards.

• Genuine lab fluency: you bring up and debug your own designs at the bench - scopes, analyzers, and methodical root-cause work.

• U.S. citizenship or permanent residency (export-controlled program - required).

GCS is acting as an Employment Business in relation to this vacancy.