Phased Array Design Engineer

GCS Recruitment; Virginia Beach (VA); Presencial; USD 120.000 - 180.000; Jornada completa

Descripción de la vacante

GCS Recruitment seeks an accomplished hardware design engineer to own high-speed board development for a satellite constellation project. You will design 20+ layer boards, manage schematic capture, layout ownership, bring-up in lab, and drive root-cause debugging with fast iteration.

The role emphasizes hands-on lab work, parallel design and validation across revisions, power distribution, multi-gigabit interfaces, and compliance with high-reliability aerospace standards.

Formación

• 8+ years of board-level design ownership.
• High-speed digital design including SerDes/JESD204/PCIe/DDR.
• Power-architecture for dense, high-power boards.
• Genuine lab fluency: bring up and debug designs at the bench.
• S. citizenship or permanent residency (export-controlled program).

Responsabilidades

• Design high-complexity, high-speed digital boards (20+ layer, thousands of components).
• Architect power delivery for boards with hundreds of high-performance chips.
• Design and validate multi-gigabit interfaces (SerDes, JESD204, PCIe, DDR).
• Bring up fabricated boards in the lab: first power-on, section checks, root-cause debugging.
• Run validation campaigns and feed findings into revisions.
• Select components with reliability, thermal, vibration, and radiation considerations.

Conocimientos

Board-level design

High-speed digital design

Power architecture

Lab bring-up & debug

Parallel design & validation

Herramientas

Siemens Xpedition

Altium

Cadence Allegro

Descripción del empleo

ABOUT THE PROGRAM

Our client is building one of the world's largest low-Earth-orbit satellite constellations, delivering broadband internet from space - hundreds of satellites already in orbit, thousands planned, with commercial service launching now and next-generation programs in active design. The hardware team behind it designs the electronics that drive the satellites' phased-array antennas: meter-scale, 20+ layer boards carrying custom silicon connected by ~25 Gbps high-speed serial links. Boards are designed, brought up, and validated in-house - engineers on this team see their own work fly on real satellites.

THE ROLE

You will own complex, high-speed board design in the phased-array signal chain - and see your designs through the lab. The team runs design and validation in parallel: while one board revision is being validated at the bench, the next is in design. You'll design boards (schematic capture, component selection, layout ownership), personally bring up newly fabricated hardware, debug to root cause, and feed findings into the next revision. This is a design-first seat with real lab ownership - not a test role, and not a documentation role.

WHAT YOU'LL DO

• Design high-complexity, high-speed digital boards: schematic capture, component selection, and layout ownership on 20+ layer, thousands-of-components designs built around custom silicon.
• Architect power delivery for boards carrying hundreds of high-performance chips - rail generation, sequencing, budgeting, and protection.
• Design and validate multi-gigabit interfaces (SerDes-class links, JESD204, PCIe, DDR) with disciplined signal- and power-integrity practice.
• Bring up newly fabricated boards in the lab: first power-on, section-by-section checkout, root-cause debug with oscilloscopes and high-speed instrumentation.
• Run validation campaigns proving designs meet requirements, and feed every finding into the next board revision.
• Select components with reliability, thermal, vibration, and radiation considerations in partnership with specialist review teams.

REQUIRED EXPERIENCE

• 8+ years of board-level design ownership - complex boards you can point to and say "mine": schematic, component selection, and layout.
• High-speed digital design: SerDes, JESD204, PCIe, and/or DDR, with hands-on signal-integrity practice (controlled impedance, length matching, stackup design).
• Power-architecture design for dense, high-power boards.
• Genuine lab fluency: you bring up and debug your own designs at the bench - scopes, analyzers, and methodical root-cause work.
• S. citizenship or permanent residency (export-controlled program - required).

NICE TO HAVE

• Space, aerospace, or defense high-reliability experience - DO-254/DO-160, MIL-STD, derating, worst-case analysis, radiation-aware design.
• Experience with Siemens Xpedition (Altium or Cadence Allegro equally welcome).
• Phased-array, radar, satellite, or other RF-system board experience (the boards, not the antennas).
• Experience working design/validation in parallel across board revisions.