Staff GPU RTL Power Engineer — Powering Mobile GPUs

Samsung Electronics Perú; Austin (TX); On-site; USD 151,000 - 227,000; Full time

Benefits offered by this job

Medical

Dental

Vision

Life insurance

401(k)

Onsite lunch

Employee purchase program

Tuition assistance

Paid time off

Student loan program

Wellness incentives

Job summary

Samsung Austin Research and Development Center (SARC) is seeking a Staff GPU RTL Design Engineer to contribute to power management RTL blocks for next-gen mobile GPU IPs. You will collaborate with hardware and software teams, driving RTL development from microarchitecture through verification to ensure scalable, production-ready designs.

You will leverage Verilog/SystemVerilog expertise, apply microarchitectural understanding, and work across IP generations to optimize power, timing, and area

Qualifications

• 6+ years with a Bachelor's Degree in Computer Science/Engineering, or 4+ years with a Master’s, or 2+ years with a Ph.D.
• 4+ years of hands-on experience in power management or low power microarchitecture design for complex SoC, CPU, or GPU architectures.
• Hands-on experience in RTL design using Verilog/SystemVerilog, including microarchitecture development, integration, and debug.

Responsibilities

• Design and develop power management RTL blocks and subsystems for mobile GPU IPs.
• Collaborate with hardware and software teams to enable GPU feature implementations.
• Support verification, integration, and debugging to ensure robust, production-ready designs.

Skills

RTL design

Verilog/SystemVerilog

Power management

GPU architecture

Python/Perl scripting

Team collaboration

Communication skills

Education

Bachelor's in CS/Engineering

Master's in CS/Engineering

Tools

Python

Perl

Job description

Samsung Austin Research and Development Center (SARC) is seeking a Staff GPU RTL Design Engineer to contribute to power management RTL blocks for next-gen mobile GPU IPs. You will collaborate with hardware and software teams, driving RTL development from microarchitecture through verification to ensure scalable, production-ready designs.

You will leverage Verilog/SystemVerilog expertise, apply microarchitectural understanding, and work across IP generations to optimize power, timing, and area