Senior GPU RTL Power Management Engineer

Samsung Electronics; Austin (TX); On-site; USD 151,000 - 227,000; Full time

Benefits offered by this job

Medical

Dental

Vision

Life Insurance

401(k)

Onsite lunch

Employee purchase program

Tuition assistance

Paid time off

Student loan

Wellness incentives

MBO bonus

Long-term incentive plan

Relocation

Job summary

Samsung Austin Research and Development Center (SARC) and ACL are building a center of excellence for IP powering next‑generation mobile GPUs. As a Staff GPU RTL Design Engineer, you will develop power management RTL blocks and interfaces for Samsung's mobile GPU IPs, collaborating with hardware and software teams.

This mid‑to‑senior IC role emphasizes microarchitecture to RTL, design quality, verification collaboration, and scalable, production‑ready implementations that enable energy‑efficient

Qualifications

• BS in Computer Science/Engineering (or MS/PhD equivalents)
• 4+ years in power management or low-power microarchitecture design for complex SoCs/GPUs
• RTL design with Verilog/SystemVerilog (microarchitecture, integration, debug)
• GPU/SoC power management knowledge: IP power seq, clock/reset, DVS
• Python/Perl scripting
• Strong analytical and communication skills

Responsibilities

• Contribute to microarchitecture definition and RTL implementation of power management GPU blocks and subsystems.
• Drive RTL design lifecycle from microarchitecture through RTL development, integration, debug, and simulation readiness.
• Collaborate with SoC, architecture, physical design, and verification teams to optimize timing, power, and area.
• Advance design practices and methodologies for GPU RTL through exploration of new technologies.

Job description

Samsung Austin Research and Development Center (SARC) and ACL are building a center of excellence for IP powering next‑generation mobile GPUs. As a Staff GPU RTL Design Engineer, you will develop power management RTL blocks and interfaces for Samsung's mobile GPU IPs, collaborating with hardware and software teams.

This mid‑to‑senior IC role emphasizes microarchitecture to RTL, design quality, verification collaboration, and scalable, production‑ready implementations that enable energy‑efficient