Senior Functional Safety Architect for Safe AI SoC

Velaura; Santa Clara (CA); On-site; USD 200,000 - 300,000; Full time

Benefits offered by this job

Equity compensation

Medical, dental, vision coverage

Flexible work arrangements

Job summary

Velaura is designing the compute silicon powering autonomous systems and safe robots. As the Functional Safety Architect for our Physical AI SoC, you will own the functional safety architecture across the silicon stack and lifecycle, ensuring safety cases meet ISO 26262 and IEC 61508 requirements.

You will partner with design, firmware, and software teams to embed safety in RTL, boot flow, and SDK, while mentoring engineers and shaping safety practices across the organization.

Qualifications

• 10+ years in functional safety or safety-critical hardware engineering.
• Experience applying ISO 26262 up to ASIL D and IEC 61508 up to SIL 3 to SoC development.
• Hands‑on experience leading safety analyses (HARA, FMEA/FMEDA, FTA, DFA).
• Experience with safety mechanisms (ECC, lockstep, BIST, redundancy, safe‑state design).
• Ability to build and defend a safety case across multi‑disciplinary teams.
• Bachelor’s or advanced degree in Electrical/Computer Engineering, Computer Science, or a related field (or equivalent practical experience).
• Excellent written and verbal communication skills, with a track record of influencing technical direction and mentoring engineers.

Responsibilities

• Own the SoC functional safety architecture: define safety goals, safety mechanisms, and the hardware/software fault-handling strategy across Velaura’s Physical AI silicon roadmap.
• Lead safety analyses—hazard analysis and risk assessment, DFMEA, FMEDA, FTA, and dependent-failure/common-cause analysis—and derive the quantitative safety metrics required by the target standard (SPFM, LFM, and PMHF for ISO 26262 ASIL; SFF, diagnostic coverage, HFT, and PFH/PFD for IEC 61508 SIL), including diagnostic-coverage targets for the SoC and its subsystems.
• Define safety mechanisms for compute, AI/NPU, memory, and interconnect including error detection and correction, lockstep, BIST, and safe-state handling, and specify the assumptions of use for the safety element out of context (SEooC).
• Partner with silicon design, firmware, safety, and platform software teams to embed safety requirements into the RTL, boot flow, and SDK, and to review implementations against the safety concept.
• Own the safety case and work products across the safety lifecycle, coordinating with assessors and customers to support certification and audits.
• Establish functional safety processes, standards, and design practices; mentor engineers and raise the safety-engineering bar across the organization.
• Manage the interface between functional safety and adjacent disciplines—cybersecurity, reliability, and SOTIF—so that safety concerns are addressed holistically.

Skills

Functional safety

Hardware engineering

Safety analyses

Communication

Mentoring

Education

Electrical/Computer Engineering degree or equivalent

Computer Science degree or equivalent

Tools

ECC

Lockstep

BIST

Redundancy

Job description

Velaura is designing the compute silicon powering autonomous systems and safe robots. As the Functional Safety Architect for our Physical AI SoC, you will own the functional safety architecture across the silicon stack and lifecycle, ensuring safety cases meet ISO 26262 and IEC 61508 requirements.

You will partner with design, firmware, and software teams to embed safety in RTL, boot flow, and SDK, while mentoring engineers and shaping safety practices across the organization.