Senior Frontend Chip Design Engineer (RTL)

Cerebras Systems; Sunnyvale (CA); Hybrid; USD 250,000 - 300,000; Full time

Benefits offered by this job

Hybrid work environment

Job summary

Cerebras Systems, Sunnyvale, CA, is hiring a senior front-end design engineer to help design and deliver the Cerebras Wafer Scale Engine (WSE). You will lead RTL development, work with PD, verification, software and system teams, and coordinate with external vendors to bring innovative semiconductor architectures from concept to production.

The role requires a Master’s degree, 8+ years in RTL design, and experience with chip integration and networking; hybrid work is available, and the base

Qualifications

• Master’s degree in Computer Science, Electrical Engineering, or equivalent.
• 8+ years of experience in delivering complex, high performance RTL designs.
• Experience with Front End Chip integration and third-party IP integration.
• Networking stack experience including TCP/IP, RDMA and Ethernet.

Responsibilities

• Drive all aspects of chip design, including Functional Specification, Micro-architecture, RTL development, Synthesis.
• Work with PD, design verification, software and system teams to meet PPA goals.
• Collaborate with external vendors to deliver silicon.
• Debug silicon-level functional, timing, and power issues during bring up.

Skills

RTL design

System integration

Scripting (Python, TCL)

Networking/PCIe/Serdes

External vendor collaboration

Education

Master’s degree

Tools

FPGA toolchain

Job description

Cerebras Systems, Sunnyvale, CA, is hiring a senior front-end design engineer to help design and deliver the Cerebras Wafer Scale Engine (WSE). You will lead RTL development, work with PD, verification, software and system teams, and coordinate with external vendors to bring innovative semiconductor architectures from concept to production.

The role requires a Master’s degree, 8+ years in RTL design, and experience with chip integration and networking; hybrid work is available, and the base