Senior Front End Design Engineer – Microarchitecture & RTL

Cerebras; Sunnyvale (CA); Hybrid; USD 250,000 - 300,000; Full time

Job summary

The Cerebras Systems Senior Front-End Design Engineer role in Sunnyvale, CA, focuses on RTL design and silicon integration for the world’s largest AI chip family. You will collaborate across verification, PD, software and systems teams to deliver high-performance, power-efficient architectures from concept to production.

You should have a Master’s in CS or EE, 8+ years of RTL design experience, and a track record of silicon success, with strong TCP/IP/RDMA/Ethernet networking knowledge and

Qualifications

• Master’s degree in Computer Science, Electrical Engineering, or equivalent.
• Hybrid work environment.
• 8+ years of experience delivering complex RTL designs.
• Experience with Front End Chip integration and third-party IP integration.
• Demonstrated experience in networking, high-performance computing or related fields.
• Proven track record of multiple silicon success.
• Experience collaborating with external vendors.
• Networking stack experience including TCP/IP, RDMA and Ethernet.
• Knowledge of PCIe, CPU interfaces and Serdes technology.
• Working knowledge of scripting tools: Python, TCL.

Responsibilities

• Drive all aspects of chip design, including Functional Specification, Micro-architecture, RTL development, Synthesis.
• Work closely with PD team members for design closure to meet PPA goals.
• Work closely with Design verification and DFT teams for best functional and test coverage.
• Work with software and system teams to understand opportunities to deliver optimal performance and feature set for the product.
• Debug silicon-level functional, timing, and power issues during bring up.

Skills

RTL design

Front-end chip integration

Networking stack

Python

TCL

Education

Master’s degree in CS/EE

Tools

FPGA development toolchain

Place and Route

Timing Analysis

Job description

The Cerebras Systems Senior Front-End Design Engineer role in Sunnyvale, CA, focuses on RTL design and silicon integration for the world’s largest AI chip family. You will collaborate across verification, PD, software and systems teams to deliver high-performance, power-efficient architectures from concept to production.

You should have a Master’s in CS or EE, 8+ years of RTL design experience, and a track record of silicon success, with strong TCP/IP/RDMA/Ethernet networking knowledge and