Lead RTL Design Engineer

Cerebras Systems; Sunnyvale (CA); On-site; USD 175,000 - 275,000; Full time

Benefits offered by this job

Job stability with startup vitality

Opportunity to work on cutting-edge AI research

Open-source research publication

Job summary

A leading AI hardware company in Sunnyvale, California is looking for a lead front-end design engineer. In this role, you will focus on chip design and collaboration with various teams to innovate semiconductor architectures. Ideal candidates will have over 10 years of experience in RTL design and a master's degree in computer science or electrical engineering. The company offers a competitive salary range of $175,000 to $275,000 annually along with a modern work culture.

Qualifications

• 10+ years of experience in delivering complex, high performance RTL designs.
• Experience collaborating and managing external vendors.
• Knowledge of PCIe, CPU interfaces and Serdes technology.

Responsibilities

• Drive all aspects of chip design including RTL development.
• Manage external ASIC vendor through product development cycle.
• Collaborate with teams to deliver optimal performance and feature set.

Skills

RTL design

Front End Chip integration

Networking

High-performance computing

Machine learning

Python

TCL

Education

Master’s degree in Computer Science or Electrical Engineering

Tools

FPGA development toolchain

Job description

Cerebras Systems builds the world's largest AI chip, 56 times larger than GPUs. Our novel wafer-scale architecture provides the AI compute power of dozens of GPUs on a single chip, with the programming simplicity of a single device. This approach allows Cerebras to deliver industry-leading training and inference speeds and empowers machine learning users to effortlessly run large-scale ML applications, without the hassle of managing hundreds of GPUs or TPUs.

Cerebras' current customers include global corporations across multiple industries, national labs, and top-tier healthcare systems. In January, we announced a multi-year, multi-million-dollar partnership with Mayo Clinic, underscoring our commitment to transforming AI applications across various fields. In August, we launched Cerebras Inference, the fastest Generative AI inference solution in the world, over 10 times faster than GPU-based hyperscale cloud inference services.

About The Role

As a lead front-end design engineer, you will be a key part of the world-class team designing and developing the next generations of the Cerebras Wafer Scale Engine (WSE). This role requires deep expertise in RTL design and integration, with a strong focus on delivering high-performance, power-efficient, and scalable solutions. The role also requires close collaboration and management of external ASIC vendor. You will collaborate closely with the design verification, physical design, software and system teams to bring innovative semiconductor architectures from concept to production, addressing the unique challenges of building WSE systems.

Responsibilities

• Drive all aspects of chip design, including Functional Specification, Micro-architecture, RTL development, Synthesis.
• Managing external ASIC vendor through product development cycle.
• Work closely with PD team members for design closure to meet PPA goals.
• Work closely with Design verification and DFT teams for achieving the best functional and test coverage.
• Work with software and system teams to understand opportunities to deliver optimal performance and feature set for the product.
• Debug silicon-level functional, timing, and power issues during bring up.

Requirements

• Master’s degree in Computer Science, Electrical Engineering, or equivalent.
• Can work in a hybrid work environment.
• 10+ years of experience in delivering complex, high performance high quality RTL designs.
• Experience with Front End Chip integration and third-party IP integration.
• Demonstrated experience in networking, high-performance computing, machine learning or related fields.
• ven track record of multiple silicon success.
• Experience collaborating and managing external vendors.
• Experience with designing/integrating high speed IO.
• Networking stack experience including TCP/IP, RDMA and Ethernet.
• Knowledge of PCIe, CPU interfaces and Serdes technology.
• Working knowledge of scripting tools: Python, TCL.

Experience with FPGA development toolchain, including Place and Route, Floor planning and Timing Analysis is a plus.

The base salary range for this position is $175,000 to $275,000 annually. Actual compensation may include bonus and equity, and will be determined based on factors such as experience, skills, and qualifications.

Why Join Cerebras

• Build a breakthrough AI platform beyond the constraints of the GPU.
• Publish and open source their cutting-edge AI research.
• Work on one of the fastest AI supercomputers in the world.
• Enjoy job stability with startup vitality.
• Our simple, non-corporate work culture that respects individual beliefs.

Cerebras Systems is committed to creating an equal and diverse environment and is proud to be an equal opportunity employer. We celebrate different backgrounds, perspectives, and skills. We believe inclusive teams build better products and companies. We try every day to build a work environment that empowers people to do their best work through continuous learning, growth and support of those around them.

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