Senior Design Automation Engineer - Front End Design Verification

Dormont Manufacturing Co; San Jose (CA); On-site; USD 178,900 - 259,000; Full time

Job summary

Altera is seeking a Senior Design Automation Engineer to join our Design Methodology, Automation and Infrastructure Team. You will contribute to building and maintaining automated design flows from RTL to GDSII, accelerating development cycles for next-generation FPGA products.

You will develop scripts and automation frameworks, evaluate EDA tools, and collaborate with design and verification teams to remove bottlenecks and improve throughput through AI-assisted workflows.

Qualifications

• Bachelor’s or Master’s Degree in Computer Science, Electrical Engineering, or related field; 8+ years of relevant industry experience.
• Hands-on experience with Front End RTL and/or Design Verification EDA tools and FPGA/ASIC design flows (e.g., VCS, Xcelium, SpyGlass).
• Experience using AI/ML-driven features within commercial EDA tools and/or building data pipelines for learning-based design automation.
• Proficiency in Unix/Linux environments and scripting languages such as Python, Tcl, and Shell.
• Experience building flow automation tools and integrating them into complex design pipelines.
• Ability to collaborate with cross-functional teams and translate user requirements into scalable solutions.

Responsibilities

• Develop, deploy, and support advanced design automation flows and methodologies for digital semiconductor design.
• Create scripts, tooling customizations, and automation frameworks leveraging AI-driven tools to streamline complex design processes.
• Evaluate, integrate, and enhance EDA tools to improve design productivity, efficiency, and quality across the organization.
• Automate repetitive design tasks, delivering robust, scalable, maintainable solutions.
• Collaborate with design and verification teams to identify bottlenecks and implement improvements.
• Drive continuous improvement in design automation infrastructure and best practices.
• Work with internal teams and external EDA vendors to resolve tool issues and influence roadmaps.

Skills

Cross-functional collaboration

Communication

Problem solving

Education

Bachelor's or Master's in CS/EE or related field

Tools

Python

Tcl

Shell

Unix/Linux

VCS (Git)

Xcelium

SpyGlass

Job description

Job Details:

Job Description:

About Altera

Altera is at the forefront of enabling the future of advanced semiconductor solutions. We specialize in delivering world-class programmable logic devices, embedded systems, and high-performance accelerators that power cutting-edge applications across telecommunications, data centers, aerospace, and emerging AI workloads. Our culture thrives on innovation, collaboration, and excellence — empowering talented engineers to design breakthrough technologies that shape tomorrow.

Join us in our journey to becoming the world’s #1 FPGA company!

About the Role

Altera is seeking a Senior Design Automation Engineer to join our Design Methodology, Automation and Infrastructure Team.

This team is responsible for building and maintaining the core automation infrastructure that supports Altera’s FPGA design flows—from RTL to GDSII. In this role, you will play a critical part in scaling our internal design productivity, delivering highly automated, reliable, and efficient flow systems that accelerate development cycles for next-generation FPGA products.

Key Responsibilities of the Senior Design Automation Engineer include but are not limited to:

• Develop, deploy, and support advanced design automation flows and methodologies for digital semiconductor design.

• Create scripts, tooling customizations, and automation frameworks leveraging AI-driven tools and systems to streamline complex design processes.

• Evaluate, integrate, and enhance EDA tools to improve design productivity, efficiency, and quality across the organization.

• Automate repetitive design tasks, delivering solutions that are robust, scalable, maintainable, and aligned with long-term architecture.

• Collaborate with design and verification teams to identify workflow bottlenecks and implement impactful process improvements.

• Drive continuous improvement in design automation infrastructure, methodologies, and best practices.

• Work closely with internal teams and external EDA vendors to resolve tool issues, influence roadmaps, and adopt new capabilities.

Salary Range

The pay range below is for Bay Area California only. Actual salary may vary based on factors including job location, job-related knowledge, skills, experiences, trainings, etc. We also offer incentive opportunities that reward employees based on individual and company performance.

$178,900 - $259,000 USD

We use artificial intelligence to screen, assess, or select applicants for the position. Applicants must be eligible for any required U.S. export authorizations.

Qualifications:

Minimum Qualifications:

Bachelor’s or Master’s Degree in Computer Science, Electrical Engineering, or related field with 8+ years of relevant industry experience, including:

• Hands-on experience with Front End RTL and or Design Verification EDA tools and FPGA/ASIC design flows (e.g., VCS, Xcelium, SpyGlass).

• Experience utilizing AI/ML-driven features within commercial EDA tools and/or building data pipelines and training systems to support learning-based design automation.

• Proficiency in Unix/Linux environments and scripting/programming languages such as Python, Tcl, and Shell.

• Experience building flow automation tools and integrating them into complex design pipelines.

• Ability to collaborate with cross-functional teams and translate user requirements into scalable solutions.

Preferred Qualifications:

• 10+ years of relevant industry experience with Design Automation tools

• Experience with Front End Pre-Silicon design verification flows

• Familiarity with advanced features of EDA tools like Lint/CDC/RDC etc.

• Strong communication and collaboration skills, with the ability to partner across design and CAD/EDA teams.

• Prior experience in large-scale SoC or IP development environments.

Job Type:

Regular

Shift:

Shift 1 (United States of America)

Primary Location:

San Jose, California, United States

Additional Locations:

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.