Senior Front-End Design Automation Engineer - RTL & Verification

Altera; San Jose (CA); On-site; USD 188,000 - 271,000; Full time

Job summary

Altera is seeking a Senior Design Automation Engineer to join our Design Methodology, Automation and Infrastructure Team. This role focuses on building and maintaining core automation infrastructure that supports FPGA design flows—from RTL to GDSII—and accelerating development cycles for next‑generation FPGA products.

You will develop automation flows, create scripts, evaluate EDA tools, and partner with design and verification teams to drive scalable, reliable solutions and continuous

Qualifications

• 8+ years hands-on experience with Front End RTL/Design Verification EDA tools and FPGA/ASIC design flows (e.g., VCS, Xcelium, SpyGlass).
• Experience utilizing AI/ML-driven features within commercial EDA tools and/or building data pipelines and training systems for learning-based design automation.
• Proficiency in Unix/Linux environments and scripting/programming languages such as Python, Tcl, and Shell.
• Experience building flow automation tools and integrating them into complex design pipelines.
• Ability to collaborate with cross-functional teams and translate user requirements into scalable solutions.

Responsibilities

• Develop, deploy, and support advanced design automation flows and methodologies for digital semiconductor design.
• Create scripts, tooling customizations, and automation frameworks leveraging AI-driven tools and systems to streamline complex design processes.
• Evaluate, integrate, and enhance EDA tools to improve design productivity, efficiency, and quality across the organization.
• Automate repetitive design tasks, delivering solutions that are robust, scalable, maintainable, and aligned with long-term architecture.
• Collaborate with design and verification teams to identify workflow bottlenecks and implement impactful process improvements.
• Drive continuous improvement in design automation infrastructure, methodologies, and best practices.
• Work closely with internal teams and external EDA vendors to resolve tool issues, influence roadmaps, and adopt new capabilities.

Skills

Python

Tcl

Shell

Unix/Linux

Tools

VCS

Xcelium

SpyGlass

Job description

Altera is seeking a Senior Design Automation Engineer to join our Design Methodology, Automation and Infrastructure Team. This role focuses on building and maintaining core automation infrastructure that supports FPGA design flows—from RTL to GDSII—and accelerating development cycles for next‑generation FPGA products.

You will develop automation flows, create scripts, evaluate EDA tools, and partner with design and verification teams to drive scalable, reliable solutions and continuous