Senior Front End Design Engineer (Microarchitecture)

Cerebras Systems, Inc.; Sunnyvale (CA); On-site; USD 250,000 - 300,000; Full time

Benefits offered by this job

Job stability with startup vitality

Non-corporate work culture

Opportunities for continuous learning and growth

Job summary

Cerebras Systems, Inc. is seeking a Senior Front-End Design Engineer in Sunnyvale, CA. This role involves designing the next generations of the Cerebras Wafer Scale Engine, with a focus on high-performance and power-efficient solutions. You will work with cross-functional teams to tackle the unique challenges associated with innovative semiconductor architectures.

The ideal candidate should have a Master’s degree and 8+ years of experience in high-quality RTL designs, emphasizing collaboration and technical expertise in networking and high-performance computing.

Qualifications

• 8+ years of complex RTL design experience required.
• Proficient in networking and high-performance computing.
• Experience with front-end chip integration and external vendor collaboration.

Responsibilities

• Drive chip design aspects, including RTL development and synthesis.
• Collaborate with PD and verification teams for design closure.
• Debug silicon-level functional and timing issues as necessary.

Skills

RTL design

Integration

Debugging

Collaboration

Scripting tools (Python, TCL)

Education

Master’s degree in Computer Science or Electrical Engineering

Tools

FPGA development toolchain

Networking stack (TCP/IP, RDMA, Ethernet)

Job description

Cerebras Systems builds the world's largest AI chip, 56 times larger than GPUs. This architecture allows Cerebras to deliver industry-leading training and inference speeds; over 10 times faster than GPU-based hyperscale cloud inference services.

This order of magnitude increase in speed is transforming the user experience of AI applications, unlocking real-time iteration and increasing intelligence via additional agentic computation.

Cerebras works with the leading model labs, global enterprises, and cutting-edge AI-native startups. OpenAI recently announced a multi-year partnership with Cerebras, to deploy 750 megawatts of scale, transforming key workloads with ultra high-speed inference.

About The Role

As a senior front-end design engineer, you will be a key part of the world-class team designing and developing the next generations of the Cerebras Wafer Scale Engine (WSE). This role requires deep expertise in RTL design and integration, with a strong focus on delivering high-performance, power-efficient, and scalable solutions. You will collaborate closely with the design verification, physical design, software and system teams to bring innovative semiconductor architectures from concept to production, addressing the unique challenges of building WSE systems.

Responsibilities

• Drive all aspects of chip design, including Functional Specification, Micro‑architecture, RTL development, Synthesis.
• Work closely with PD team members for design closure to meet PPA goals.
• Work closely with Design verification and DFT teams for achieving the best functional and test coverage.
• Work with software and system teams to understand opportunities to deliver optimal performance and feature set for the product.
• Debug silicon‑level functional, timing, and power issues during bring up.

Requirements

• Master’s degree in Computer Science, Electrical Engineering, or equivalent.
• Can work in a hybrid work environment.
• 8+ years of experience in delivering complex, high performance high quality RTL designs.
• Experience with Front End Chip integration and third‑party IP integration.
• Demonstrated experience in networking, high-performance computing, machine learning or related fields.
• Proven track record of multiple silicon success.
• Experience collaborating with external vendors.
• Networking stack experience including TCP/IP, RDMA and Ethernet.
• Knowledge of PCIe, CPU interfaces and Serdes technology.
• Working knowledge of scripting tools : Python, TCL.

Assets

• Experience with FPGA development toolchain, including Place and Route, Floor planning and Timing Analysis is a plus.
• Experience managing external ASIC vendor through product development cycle.

Location: Sunnyvale, CA

The base salary range for this position is $250,000 to $300,000 annually. Actual compensation may include bonus and equity, and will be determined based on factors such as experience, skills, and qualifications.

Why Join Cerebras

1. Build a breakthrough AI platform beyond the constraints of the GPU.
2. Publish and open source their cutting‑edge AI research.
3. Work on one of the fastest AI supercomputers in the world.
4. Enjoy job stability with startup vitality.
5. Our simple, non‑corporate work culture that respects individual beliefs.

Find out more about what it's like to work at Cerebras here!

Apply today and become part of the forefront of groundbreaking advancements in AI!

Cerebras Systems is committed to creating an equal and diverse environment and is proud to be an equal opportunity employer. We celebrate different backgrounds, perspectives, and skills. We believe inclusive teams build better products and companies. We try every day to build a work environment that empowers people to do their best work through continuous learning, growth and support of those around them.

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