Senior FPGA Verification & Pre-Sales Engineer

Synopsys Inc; Sunnyvale (CA); On-site; USD 180,000 - 240,000; Full time

Job summary

Synopsys is seeking a senior hardware verification strategist in Sunnyvale to lead pre‑sales engagements for ZeBu, ZS5 Emulation, and HAPS FPGA prototyping. You will tailor solutions, run proofs‑of‑concepts, and drive technical wins by demonstrating real value to customers.

You will guide evaluations, collaborate with sales, and translate complex prototyping challenges into business impact, shaping opportunities and advancing ROC for AI‑enabled design validation.

Qualifications

• 10–12 years hands-on experience in emulation, FPGA‑based prototyping, ASIC/SoC validation.
• Deep understanding of RTL‑to‑hardware workflows and associated design challenges.
• Comfort with travel to customer sites for evaluations and engagements.
• Experience with ZeBu, HAPS platforms, ProtoCompiler or similar tools is highly desirable.

Responsibilities

• Lead pre-sales technical engagements for ZeBu-200, ZS5 Emulation, and HAPS FPGA prototyping platforms.
• Present tailored hardware‑assisted verification solutions addressing partitioning, performance, debug, and RTL/simulation integration.
• Conduct technical evaluations, proofs‑of‑concept projects, and benchmarks to demonstrate real value.

Skills

FPGA prototyping

Emulation

Verilog/VHDL

RTL-to-hardware workflows

Xilinx/Intel FPGA

Pre-sales

Customer engagements

Benchmarks & data

Travel readiness

Proof-of-concept

Education

Bachelor's or Master's in Electronics/Computer Engineering

Tools

ZeBu

HAPS

ProtoCompiler

Job description

Synopsys is seeking a senior hardware verification strategist in Sunnyvale to lead pre‑sales engagements for ZeBu, ZS5 Emulation, and HAPS FPGA prototyping. You will tailor solutions, run proofs‑of‑concepts, and drive technical wins by demonstrating real value to customers.

You will guide evaluations, collaborate with sales, and translate complex prototyping challenges into business impact, shaping opportunities and advancing ROC for AI‑enabled design validation.