Senior FPGA Verification Lead — UVM Architect

L3Harris Technologies; Palm Bay (FL); On-site; USD 140,000 - 190,000; Full time

Job summary

L3Harris Technologies seeks a Lead FPGA Verification engineer in Palm Bay, FL to drive UVM-based validation of complex FPGA designs. You will develop reusable testbenches, drive coverage goals, and collaborate with design and systems teams to ensure functional correctness throughout the lifecycle.

Ideal candidates bring SystemVerilog expertise, constrained random verification experience, and strong scripting skills.

Qualifications

• Experience with SystemVerilog-based verification and assertions.
• Strong problem-solving skills and debugging across regression suites.
• Familiarity with constrained-random testbenches and coverage metrics.

Responsibilities

• Execute and contribute to FPGA verification plan.
• Architect UVM test cases for blocks within FPGA.
• Develop reusable agents, top-level testbenches, and environments.
• Define functional coverage based on DUT requirements and achieve coverage goals.
• Create drivers, monitors, predictors, and scoreboards using UVM.

Skills

UVM verification

SystemVerilog

Python scripting

C/C++

Education

Bachelor’s Degree + 9+ years experience

Tools

Vivado

Quartus

Job description

L3Harris Technologies seeks a Lead FPGA Verification engineer in Palm Bay, FL to drive UVM-based validation of complex FPGA designs. You will develop reusable testbenches, drive coverage goals, and collaborate with design and systems teams to ensure functional correctness throughout the lifecycle.

Ideal candidates bring SystemVerilog expertise, constrained random verification experience, and strong scripting skills.