Senior FPGA Verification Engineer – Spaceflight

Blue Origin; Seattle (WA); On-site; USD 131,000 - 183,000; Full time

Benefits offered by this job

Medical, dental, vision

401(k) with company match

Paid parental leave

Stock options

Paid time off

Job summary

Blue Origin, based in Washington, seeks an FPGA verification engineer to verify FPGAs/ASICs for our lunar landing systems. You will develop testbenches, plans, and tests to meet functional and system-level coverage goals using UVM and SystemVerilog.

The role requires 5+ years of FPGA/ASIC verification, RTL simulation with QuestaSim/ModelSim, and knowledge of DO-254 is a plus. Collaboration within Sustaining Lunar Development is essential, with risk-driven verification for safety-critical

Qualifications

• BS/MS in Electrical Engineering, Computer Engineering or a closely related field of study.
• 5+ years experience verifying FPGAs or ASICs
• In-depth experience using RTL simulation tools such as Siemens QuestaSim, ModelSim, or equivalent
• In-depth knowledge of System Verilog and the Universal Verification Methodology (UVM).
• Expertise in developing testbench environment and verification components (Monitor, Scoreboard, Driver, Agent etc.) from scratch.
• Understands different types of coverage, usage of cover classes, cover points, etc.
• Experience with predictive testbench components, functional coverage and assertions.
• Experience with constrained random verification. Experience with the Register Abstraction Layer.
• Develop detailed test plans and write tests, run regressions, collect coverage matrices and report progress to the program
• Reviewing verification and validation results against the coverage goals.
• Writing, analyzing and achieving coverage metrics.
• Experience of debugging skills to narrow down and isolate issue between RTL design and testbench or test case is required.

Responsibilities

• Perform requirements-based verification of FPGAs using Universal Verification Methodology (UVM).
• Create comprehensive verification and validation plan that encompasses functional and system level verification and validation.
• Develop IP/subsystem/system level testbench and tests to achieve required coverage goals.
• Document plans and procedures.
• Write directed and random test cases.
• Generate reports in support of certification of the design to a high DAL.

Skills

UVM

SystemVerilog

Testbench development

Coverage concepts

Constrained random

RTL verification

Education

BS/MS in Electrical/Computer Engineering or related

Tools

QuestaSim

ModelSim

Verilog/SystemVerilog tools

Job description

Blue Origin, based in Washington, seeks an FPGA verification engineer to verify FPGAs/ASICs for our lunar landing systems. You will develop testbenches, plans, and tests to meet functional and system-level coverage goals using UVM and SystemVerilog.

The role requires 5+ years of FPGA/ASIC verification, RTL simulation with QuestaSim/ModelSim, and knowledge of DO-254 is a plus. Collaboration within Sustaining Lunar Development is essential, with risk-driven verification for safety-critical