Senior FPGA Verification Engineer – Security-Cleared Impact

Telemetry Today LLC; Waltham (MA); On-site; USD 191,000 - 253,000; Full time

Job summary

Anduril Industries is seeking a Senior FPGA Verification Engineer to help design new product lines. You will work with an interdisciplinary technical team to define, develop, test, and mature prototypes into flight-ready hardware.

You will lead verification efforts, architect environments, develop testbenches, and contribute to estimates while advancing RTL verification across SystemVerilog and VHDL. This role requires a strong background in HDL, 8+ years of FPGA experience, and the ability to

Qualifications

• Bachelor's in Electrical/Computer Engineering or related field.
• 8+ years of HDL firmware experience for FPGA.
• Experience simulating RTL designs with VHDL/Verilog in FPGA/ASIC environments.
• Proven verification testbench design for RTL blocks (VHDL/SystemVerilog).
• Experience with chip-level verification methodologies (constrained-random testing, functional coverage, assertions).
• Experience with Git or Subversion for source code management.
• Eligible to obtain and maintain an active U.S. Secret security clearance.

Responsibilities

• Define verification environment architecture with SystemVerilog or UVM/OVM.
• Create written test plans, test cases, coverage tracking.
• Develop testbenches for RTL blocks using VHDL or SystemVerilog.
• Recommend new tools and practices to improve FPGA verification flow.
• Contribute to engineering estimates for new programs.
• Provide technical leadership for project verification teams.

Skills

HDL verification

SystemVerilog

VHDL

RTL testbenches

Leadership

Git / SVN

Education

Bachelor's in Electrical/Computer Engineering

Tools

QuestaSim

Synplify

Quartus

Vivado

Linux

Python / scripting

C/C++

Job description

Anduril Industries is seeking a Senior FPGA Verification Engineer to help design new product lines. You will work with an interdisciplinary technical team to define, develop, test, and mature prototypes into flight-ready hardware.

You will lead verification efforts, architect environments, develop testbenches, and contribute to estimates while advancing RTL verification across SystemVerilog and VHDL. This role requires a strong background in HDL, 8+ years of FPGA experience, and the ability to