Senior FPGA Verification Engineer RTL SystemVerilog Imaging

Telemetry Today LLC; Waltham (MA); On-site; USD 191,000 - 253,000; Full time

Job summary

Anduril Industries seeks a Senior FPGA Verification Engineer to drive verification for new product lines within the Imaging team. You will collaborate with interdisciplinary engineers to define, validate, and prototype designs, maturing concepts into flight-tested hardware.

The role requires extensive HDL/FPGA experience, VHDL/Verilog, and leadership in verification efforts, with a strong emphasis on testbench development and coverage analysis. US Security clearance eligibility is required.

Qualifications

• ABET/ACCA accredited degree in electrical or computer engineering or related field.
• 8+ years in HDL firmware development for FPGA devices.
• Experience simulating RTL designs using VHDL/Verilog in FPGA/ASIC environments.
• Proven RTL verification testbench design for VHDL/SystemVerilog.
• Experience with chip-level verification methodologies and constraint-random testing.
• Proficient in Git or Subversion for source control.

Responsibilities

• Architect verification environment and design using SystemVerilog or UVM.
• Create test plans, test cases, and track coverage including functional coverage.
• Develop RTL testbenches for VHDL and SystemVerilog blocks.
• Suggest tools and practices to improve FPGA/ASIC verification flow.
• Contribute to engineering estimates for new programs.
• Provide technical leadership for project verification teams.

Skills

HDL verification

FPGA design experience

VHDL/Verilog

RTL verification

Team leadership

Communication

Education

Bachelor's in Electrical Engineering or related field

Tools

Questasim

Synplify

Quartus

Vivado

Git

Job description

Anduril Industries seeks a Senior FPGA Verification Engineer to drive verification for new product lines within the Imaging team. You will collaborate with interdisciplinary engineers to define, validate, and prototype designs, maturing concepts into flight-tested hardware.

The role requires extensive HDL/FPGA experience, VHDL/Verilog, and leadership in verification efforts, with a strong emphasis on testbench development and coverage analysis. US Security clearance eligibility is required.