Senior FPGA Verification Engineer – Imaging & Defense Tech

Anduril Industries; Waltham (MA); On-site; USD 166,000 - 220,000; Full time

Job summary

Anduril Industries seeks an experienced FPGA Verification Engineer to design and mature new product lines. You will collaborate across disciplines to define, implement, build prototypes, and drive ground and flight testing toward production.

The role emphasizes verification of RTL blocks, SystemVerilog/OVM/UVM, and continuous improvement of the verification flow. A strong background in HDL, VHDL/Verilog, and security clearance is required.

Qualifications

• ABachelor’s in Electrical Engineering, Computer Engineering, or related field.
• 8+ years of experience developing HDL firmware for FPGA devices.
• Proven ability to design, implement, and execute verification testbenches for RTL blocks.
• Experience with VHDL/Verilog in FPGA/ASIC development environments.
• Experience with chip-level verification methods: constrained-random testing, functional coverage, assertion-based verification.

Responsibilities

• Define verification environment architecture using SystemVerilog/OVM/UVM.
• Create test plans, test cases, and coverage tracking.
• Develop testbenches for RTL blocks with VHDL/SystemVerilog.
• Suggest tools and practices to improve FPGA/ASIC verification flow.
• Provide technical leadership and planning for verification activities.

Skills

HDL firmware

SystemVerilog

VHDL

RTL verification

Git

Secret clearance

Education

Bachelor’s in Electrical Engineering

Tools

QuestaSim

Synplify

Quartus

Vivado

Git

Subversion

Job description

Anduril Industries seeks an experienced FPGA Verification Engineer to design and mature new product lines. You will collaborate across disciplines to define, implement, build prototypes, and drive ground and flight testing toward production.

The role emphasizes verification of RTL blocks, SystemVerilog/OVM/UVM, and continuous improvement of the verification flow. A strong background in HDL, VHDL/Verilog, and security clearance is required.