Senior FPGA Verification Engineer – Avionics, UVM & Equity

Anduril-1; Costa Mesa (CA); On-site; USD 166,000 - 220,000; Full time

Benefits offered by this job

Equity grants

Health benefits

Job summary

Anduril Industries in Costa Mesa, CA seeks a Senior FPGA Verification Engineer to own FPGA/SoC verification on AMD Xilinx platforms for flight-critical avionics. You will work with SystemVerilog, UVM, SVA and object-oriented techniques to drive coverage and ensure DO-254 compliance.

The role focuses on verification environments, test plans, and collaboration with RTL designers, with opportunities for hardware bring-up and safety-critical verification processes.

Qualifications

• Requires a Bachelor's in Electrical or Computer Engineering.
• 8+ years FPGA/ASIC verification experience.
• Proficiency in SystemVerilog, UVM, and SVA with strong testbench contributions.
• Object-oriented programming principles.
• Experience with major simulators and Git-based workflows.
• Eligible for U.S. Secret security clearance.

Responsibilities

• Architect and implement UVM verification environments for FPGA/SoC designs.
• Develop verification plans and traceability to requirements.
• Write SystemVerilog Assertions for protocol checks.
• Build coverage models and drive closure with constrained-random testing.
• Maintain regression suites and analyze verification progress.
• Collaborate with RTL designers and support hardware Bring-Up.

Skills

SystemVerilog

UVM

SVA

OO programming

Communication

Education

Bachelor's degree in Electrical/Computer Engineering

Master's degree preferred

Tools

Questa

VCS

Xcelium

Vivado

Job description

Anduril Industries in Costa Mesa, CA seeks a Senior FPGA Verification Engineer to own FPGA/SoC verification on AMD Xilinx platforms for flight-critical avionics. You will work with SystemVerilog, UVM, SVA and object-oriented techniques to drive coverage and ensure DO-254 compliance.

The role focuses on verification environments, test plans, and collaboration with RTL designers, with opportunities for hardware bring-up and safety-critical verification processes.