Senior FPGA Engineer: Space SDR & DSP

Argotec; La Mirada (CA); On-site; USD 130,000 - 190,000; Full time

Benefits offered by this job

Medical benefits

401(k) with match

Paid time off

Job summary

Argotec in California is seeking an FPGA Engineer to develop next-generation SDR communication payloads for space missions, including deep-space and lunar links. You will implement high-performance FPGA designs in Verilog/SystemVerilog or VHDL and collaborate with system, RF, hardware, and software teams.

The role emphasizes radiation-tolerant design, timing closure, DSP functions, high-speed interfaces, and lab validation.

Qualifications

• Bachelor's or Master's degree in Electrical or Computer Engineering.
• 5+ years of FPGA design experience in professional or research settings.
• U.S. Citizenship or permanent residency required.
• Excellent written and spoken English.

Responsibilities

• Develop, implement, and maintain FPGA designs using Verilog, SystemVerilog, or VHDL.
• Design DSP functions: filtering, modulation, channelization, rate conversion.
• Implement high-speed interfaces (JESD204, LVDS, Ethernet, SpaceWire).
• Perform simulation and verification with QuestaSim and Vivado Simulator; develop testbenches.
• Support synthesis, place-and-route, timing closure, and SDC constraints.
• Integrate FPGA designs with embedded processors, firmware, and software.
• Assist hardware bring-up, lab validation, debugging, and RF/system testing.
• Analyze FPGA resource use, latency, throughput, and power versus requirements.

Skills

Verilog/SystemVerilog

VHDL

DSP in FPGA

DSP algorithms

JESD204

LVDS

SpaceWire

FPGA verification

Vivado

QuestaSim

Git

Education

Electrical Engineering degree

Computer Engineering degree

Tools

Xilinx Vivado

QuestaSim

Vivado Simulator

Git

Job description

Argotec in California is seeking an FPGA Engineer to develop next-generation SDR communication payloads for space missions, including deep-space and lunar links. You will implement high-performance FPGA designs in Verilog/SystemVerilog or VHDL and collaborate with system, RF, hardware, and software teams.

The role emphasizes radiation-tolerant design, timing closure, DSP functions, high-speed interfaces, and lab validation.