FPGA Engineer – SDR Development

Argotec; La Mirada (CA); On-site; USD 130,000 - 190,000; Full time

Benefits offered by this job

Medical benefits

401(k) with match

Paid time off

Job summary

Argotec in California is seeking an FPGA Engineer to develop next-generation SDR communication payloads for space missions, including deep-space and lunar links. You will implement high-performance FPGA designs in Verilog/SystemVerilog or VHDL and collaborate with system, RF, hardware, and software teams.

The role emphasizes radiation-tolerant design, timing closure, DSP functions, high-speed interfaces, and lab validation.

Qualifications

• Bachelor's or Master's degree in Electrical or Computer Engineering.
• 5+ years of FPGA design experience in professional or research settings.
• U.S. Citizenship or permanent residency required.
• Excellent written and spoken English.

Responsibilities

• Develop, implement, and maintain FPGA designs using Verilog, SystemVerilog, or VHDL.
• Design DSP functions: filtering, modulation, channelization, rate conversion.
• Implement high-speed interfaces (JESD204, LVDS, Ethernet, SpaceWire).
• Perform simulation and verification with QuestaSim and Vivado Simulator; develop testbenches.
• Support synthesis, place-and-route, timing closure, and SDC constraints.
• Integrate FPGA designs with embedded processors, firmware, and software.
• Assist hardware bring-up, lab validation, debugging, and RF/system testing.
• Analyze FPGA resource use, latency, throughput, and power versus requirements.

Skills

Verilog/SystemVerilog

VHDL

DSP in FPGA

DSP algorithms

JESD204

LVDS

SpaceWire

FPGA verification

Vivado

QuestaSim

Git

Education

Electrical Engineering degree

Computer Engineering degree

Tools

Xilinx Vivado

QuestaSim

Vivado Simulator

Git

Job description

DUTIES & RESPONSIBILITIES

As an FPGA Engineer you will develop next-generation SDR communication payloads for future scientific missions, including deep-space, lunar, and Mars communication systems. Your FPGA designs will directly enable high-throughput waveform processing, multi-channel SDR operations, and real-time RF performance in the harsh radiation and thermal environment of space.
In this role in our California team, you will report to the Principal Embedded Systems Engineer . You will work closely with system, RF, hardware, and software engineers in a multidisciplinary environment to implement, integrate, and verify high-performance FPGA designs that support signal processing, data handling, and hardware interfaces for space SDR and telecom systems.

Specific duties include (but are not limited to):

• Develop, implement, and maintain FPGA designs using Verilog, SystemVerilog, or VHDL for space SDR and telecom systems
• Design and integrate digital signal processing (DSP) functions such as filtering, modulation/demodulation, channelization, and rate conversion
• Implement high-speed digital interfaces (e.g., JESD204, LVDS, SPI, I2C, Ethernet, SpaceWire, or similar) and ensure reliable data transfer between FPGA and peripheral devices
• Perform simulation, verification, and documentation of FPGA designs using tools such as QuestaSim, and Vivado Simulator (including testbench development and verification plans and artifacts)
• Support synthesis, place-and-route, timing closure, constraint development, and static timing analysis
• Integrate FPGA designs with embedded processors, firmware, and software; collaborate across multidisciplinary teams to deliver end-to-end system functionality
• Support hardware bring-up, lab validation, debugging, and system-level testing (including RF performance and environmental qualification)
• Analyze and optimize FPGA resource utilization, latency, throughput, and power consumption to meet system requirements
• Operate laboratory instrumentation (e.g., oscilloscopes, logic analyzers, spectrum analyzers) to support validation and debugging activities
• Develop and maintain design documentation, including requirements traceability matrices, interface control documents, and verification artifacts
• Prepare and present FPGA design details at engineering design reviews (e.g., PDR, CDR)
• Execute assigned tasks independently while coordinating priorities with technical leadership and project schedules
• Support next-generation processor selections and FPGA architecture updates

GENERAL REQUIREMENTS

• Bachelor’s or Master’s Degree in Electrical Engineering, Computer Engineering, or related fields
• At least 5+ years of experience in FPGA design and development in a professional or research environment
• U.S. Citizenship or U.S. Permanent Residency is required
• Excellent written and oral communication in English

REQUIRED EXPERIENCE & SKILLS

• Team player and a “Do what it takes” attitude
• Proficiency in Verilog, SystemVerilog, or VHDL and experience with FPGA toolchains (e.g., Xilinx Vivado) including synthesis, implementation, and timing closure
• Experience with high-speed digital interfaces (e.g., JESD204, LVDS, Ethernet, SpaceWire, or similar)
• Experience designing and implementing digital signal processing (DSP) algorithms in FPGA or fixed-point implementations
• Understanding of fixed-point arithmetic and numerical effects in FPGA implementations
• Experience with FPGA verification and validation, including simulation, testbench development, and lab bring-up/debug
• Strong understanding of digital design fundamentals, including clock domain crossing, reset strategies, IP integration, and HW/SW interfacing
• Ability to read and interpret system requirements, schematics, and interface specifications
• Strong documentation skills, including design descriptions, interface control documents, and verification reports
• Strong communication and collaboration skills in a multidisciplinary engineering environment
• Familiarity with version control systems (e.g., Git) and collaborative development workflows
• Ability to work independently with high attention to detail and ownership of assigned tasks while ensuring alignment with team objectives in a dynamic, fast-paced environment
• Analytical mind, as well as a continuous learning attitude

PREFERRED SKILLS

• Background in Space or Defense industries will be considered as a plus
• SDR architectures, digital communications systems, and RF signal processing
• Hands‑on experience with Xilinx/AMD Kintex UltraScale and/or Microchip ProAsic3 / PolarFire FPGA platforms (major plus)
• High-speed data converter interfaces (ADC/DAC) and JESD204-based systems
• Embedded processing systems (e.g., LEON, MicroBlaze, Zynq, ARM‑based SoCs)
• Understanding of radiation effects on digital designs and experience applying mitigation techniques
• Fixed‑point modeling and algorithm development in MATLAB or Python
• Hardware/software co‑design and system‑level integration, including lab validation of RF or high‑speed digital systems
• Spaceflight or high‑reliability hardware development (aerospace, defense, or similar)
• Space communications and aerospace standards (e.g., CCSDS, ECSS, ETSI, NASA)
• Strong problem‑solving skills and adaptability across HW/SW/FW boundaries

IMPORTANT NOTICE

To conform to U.S. Government international trade regulations, the applicant must be a U.S. Citizen, lawful permanent resident of the U.S., protected individual as defined by 8 U.S.C. 1324b(a)(3), or eligible to obtain the required authorizations from the U.S. Department of State or U.S. Department of Commerce.

ARGOTEC OFFERS

• Annual incentive pay is based upon performance and commensurate with the level of the position.
• Generous benefit package, including medical, dental, and vision plans, 401(k) with 100% match up to 8%, life insurance, 3 weeks paid time off, tuition reimbursement, and more.

As an Equal Opportunity Employer, this announcement is aimed at both sexes, under laws 903/77 and 125/91, and to people of all ages and all nationalities, under legislative decrees 215/03 and 216/03. Argotec is committed to fostering an inclusive, accepting, and diverse environment free of discrimination based on race, color, age, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran.